www.fairchildsemi.com
FMS3818
Triple Video D/A Converters
3 x 8 bit, 180 Ms/s
Features
•
•
•
•
•
±2.5% gain matching
±0.5 LSB linearity error
Internal bandgap voltage reference
Low glitch energy
Single 3.3 Volt power supply
Description
The FMS3818 is a low-cost triple D/A converter, tailored to
fit graphics and video applications where speed is critical.
CMOS-level inputs are converted to analog current outputs
that can drive 25–37.5Ω loads corresponding to doubly-termi-
nated 50–75Ω loads. A sync current following SYNC input
timing is added to the I
OG
output. BLANK will override
RGB inputs, setting I
OG
, I
OB
and I
OR
currents to zero when
BLANK = L. Although appropriate for many applications
the internal 1.25V reference voltage can be overridden by the
V
REF
input.
Few external components are required, just the current
reference resistor, current output load resistors, bypass
capacitors and decoupling capacitors.
Package is a 48-lead LQFP. Fabrication technology is
CMOS. Performance is guaranteed from 0 to 70°C.
Applications
• PC Graphics
• Video signal conversion
– RGB
– YC
B
C
R
– Composite, Y, C
Block Diagram
SYNC
BLANK
SYNC
I
OS
G
7-0
8
8 bit D/A
Converter
IO
G
B
7-0
8
8 bit D/A
Converter
IO
B
R
7-0
CLK
8
8 bit D/A
Converter
IO
R
COMP
R
REF
V
REF
+1.25V
Ref
REV. 1.2.3 December 2004
FMS3818
DATA SHEET
Functional Description
Within the FMS3818 are three identical 8-bit D/A
converters, each with a current source output. External loads
are required to convert these currents to voltage outputs.
Data inputs RGB
7-0
are overridden by the BLANK input.
SYNC = H activates sync current from I
OS
for sync-on-
green video signals.
V
DDA
I
OS
SYNC
G
7-0
V
DDA
BLANK gates the D/A inputs. If BLANK = H, the D/A
inputs control the output currents to be added to the output
blanking level. If BLANK = L, data inputs and the pedestal
are disabled.
D/A Outputs
Each D/A output is a current source from the V
DDA
supply.
Expressed in current units, the GBR transformation from
data to current is as
follows:
G = G
7-0
& BLANK + SYNC * 112
B = B
7-0
& BLANK
R = R
7-0
& BLANK
Typical LSB current step is 73.2 µA.
V
DDA
B
7-0
To obtain a voltage output, a resistor must be connected to
ground. Output voltage depends upon this external resistor,
the reference voltage, and the value of the gain-setting resis-
tor connected between R
REF
and GND.
To implement a doubly-terminated 75Ω transmission line, a
shunt 75Ω resistor should be placed adjacent to the analog
output pin. With a terminated 75Ω line connected to the
analog output, the load on the FMS3818 current source is
37.5Ω.
The FMS3818 may also be operated with a single 75 Ohm
terminating resistor. To lower the output voltage swing to the
desired range, the nominal value of the R
REF
resistor should
be doubled.
V
DDA
R
7-0
Figure 1. FMS3818 Current Source Structure
Voltage Reference
Full scale current is a multiple of the current I
SET
through an
external resistor, R
SET
connected between the R
REF
pin and
GND. Voltage across R
SET
is the reference voltage, V
REF
,
which can be derived from either the 1.25 volt internal
bandgap reference or an external voltage reference
connected to V
REF
. To minimize noise, a 0.1µF capacitor
should be connected between V
REF
and ground.
I
SET
is mirrored to each of the GBR output current sources.
To minimize noise, a 0.1µF capacitor should be connected
between the COMP pin and the analog supply voltage V
DDA
.
Digital Inputs
Incoming GBR data is registered on the rising edge of the
clock input, CLK. Analog outputs follow the rising edge of
CLK after a delay, t
DO
.
SYNC and BLANK
SYNC and BLANK inputs control the output level (Figure 1
and Table 1) of the D/A converters during CRT retrace
intervals. BLANK forces the D/A outputs to the blanking
level while SYNC = L turns off a current source, I
OS
that is
connected to the green D/A converter. SYNC = H adds a
112/256 fraction of full-scale current to the green output.
SYNC = L extinguishes the sync current during the sync tip.
Power and Ground
Required power is a single +3.3 Volt supply. To minimize
power supply induced noise, analog +3.3V should be
connected to V
DDD
and V
DDA
pins with 0.1 and 0.01 µF
decoupling capacitors placed adjacent to each V
DD
pin or
pin pair.
High slew-rate digital data makes capacitive coupling to the
outputs of any D/A converter a potential problem. Since the
digital signals contain high-frequency components of the
CLK signal, as well as the video output signal, the resulting
data feedthrough often looks like harmonic distortion or
reduced signal-to-noise performance. All ground pins should
be connected to a common solid ground plane for best
performance.
REV. 1.2.3 December 2004
data: 700 mV max.
sync: 307 mV
Figure 2. Nominal Output Levels
2
DATA SHEET
FMS3818
Table 1. Output Voltage Coding
V
REF
= 1.25 V, R
REF
= 348
Ω,
R
L
= 37.5
Ω
RGB7-0 (MSB…LSB)
1111 1111
1111 1111
1111 1110
1111 1101
•
•
1000 0000
0111 1111
0111 1111
•
•
0000 0010
0000 0001
0000 0000
0000 0000
XXXX XXXX
XXXX XXXX
SYNC
1
0
1
1
•
•
1
1
0
•
•
1
1
1
0
1
0
BLANK
1
1
1
1
•
•
1
1
1
•
•
1
1
1
1
0
0
V
RED
, V
BLUE
(mV)
700
700
697
695
•
•
351
349
349
•
•
5
3
0
0
0
0
V
GREEN
(mV)
1,007
700
1,004
1,001
•
•
658
656
349
•
•
312
310
307
0
307
0
Pin Assignments
LQFP Package
GND
R7
R6
R5
R4
R3
R2
R1
R0
GND
GND
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
G0
G1
G2
G3
G4
G5
G6
G7
BLANK
SYNC
VDDD
1
2
3
4
5
6
7
8
9
10
11
12
FMS3818
RREF
VREF
COMP
IOR
IOG
VDDA
VDDA
IOB
GND
GND
CLK
NC
NC
GND
GND
B0
B1
B2
B3
B4
B5
B6
B7
NC
13
14
15
16
17
18
19
20
21
22
23
24
REV. 1.2.3 December 2004
3
FMS3818
DATA SHEET
Pin Descriptions
Pin
Name
CLK
Pin Number
26
Value
CMOS
Pin Function Description
Clock Input.
Pixel data is registered on the rising edge of CLK. CLK
should be driven by a dedicated buffer to avoid reflection induced jitter,
overshoot, and undershoot.
Red, Green, and Blue Pixel Data Inputs.
RGB digital inputs are
registered on the rising edge of CLK.
Clock and Data Inputs
R
7-0
G
7-0
B
7-0
Controls
SYNC
47-40
9-2
23-16
11
CMOS
CMOS
Sync Pulse Input.
Bringing SYNC LOW, disables a current source which
superimposes a sync pulse on the I
OG
output. SYNC and pixel data are
registered on the rising edge of CLK. SYNC does not override any other
data and should be used only during the blanking interval. If sync pulses
are not required, SYNC should be connected to GND.
Blanking Input.
When BLANK is LOW, pixel data inputs are ignored and
the D/A converter outputs are driven to the blanking level. BLANK is
registered on the rising edge of CLK.
Red, Green, and Blue Current Outputs.
Current source outputs can
drive VESA VSIS, and RS-343A/SMPTE-170M compatible levels into
doubly-terminated 75 Ohm lines. Sync pulses can be added to the green
output. When SYNC is HIGH, the current added to I
OG
is:
IO
S
= 2.33 (V
REF
/ R
REF
)
BLANK
10
CMOS
Video Outputs
I
OR
I
OG
I
OB
33
32
29
0.700 V
p-p
Voltage Reference
V
REF
35
+1.25 V
Voltage Reference Input/Output.
Internal 1.25V voltage reference is
available on this pin. An external +1.25 Volt reference may be applied to
this pin to override the internal reference. Decoupling V
REF
to GND with
a 0.1µF ceramic capacitor is required.
Current-set Resistor Node.
Full-scale output current of each D/A
converter is determined by the value of the resistor connected between
R
REF
and GND. Nominal value of R
REF
is found from:
R
REF
= 5.31 (V
REF
/I
FS
)
where I
FS
is the full-scale output current (amps) from the
D/A converter (without sync). Sync is 0.439 I
FS
.
D/A full-scale current may also be calculated from:
I
FS
= V
FS
/R
L
Where V
FS
is the full-scale voltage level and R
L
is the total resistive load
(ohms) on each D/A converter.
COMP
34
0.1 µF
Compensation Capacitor Node.
A 0.1 µF ceramic capacitor must be
connected between COMP and V
DD
to stabilize internal bias circuitry.
R
REF
36
348
Ω
4
REV. 1.2.3 December 2004
DATA SHEET
FMS3818
Pin Descriptions
(continued)
Pin
Name
V
DDA
V
DDD
GND
NC
Pin Number
30, 31
12
1, 14, 15, 27,
28, 38, 39, 48
13, 24, 25, 37
Value
+3.3V
+3.3V
0.0V
—
Pin Function Description
Analog Supply Voltage.
Digital Supply Voltage.
Ground.
No Connect
Power, Ground
REV. 1.2.3 December 2004
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
