June 1997
NDS8961
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description
SO-8 N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance.These devices are particularly
suited for low voltage applications such as DC motor control
and DC/DC conversion where fast switching, low in-line power
loss, and resistance to transients are needed.
Features
3.1 A, 30 V. R
DS(ON)
= 0.1
Ω
@ V
GS
= 10 V
R
DS(ON)
= 0.15
Ω
@ V
GS
= 4.5 V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
____________________________________________________________________________________________
5
6
7
8
4
3
2
1
Absolute Maximum Ratings
T
A
= 25°C unless otherwise noted
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
(Note 1a)
NDS8961
30
±20
3.1
10
2
1.6
1
0.9
-55 to 150
Units
V
V
A
W
T
J
,T
STG
R
θ
JA
R
θ
JC
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
40
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS8961 Rev.D
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
Gate Threshold Voltage
Static Drain-Source On-Resistance
V
GS
= 0 V, I
D
= 250 µA
V
DS
= 24 V, V
GS
= 0 V
T
J
= 55
o
C
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
T
J
= 125
o
C
V
GS
= 10 V, I
D
= 3.1 A
T
J
= 125 C
V
GS
= 4.5 V, I
D
= 2.6 A
I
D(on)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 10 V,
I
D
= 3.1 A, V
GS
= 10 V
V
DD
= 10 V, I
D
= 1 A,
V
GS
= 10 V, R
GEN
= 6
Ω
V
GS
= 10 V, V
DS
= 5 V
V
GS
= 4.5 V, V
DS
= 5 V
V
DS
= 10 V, I
D
= 3.1 A
V
DS
= 15 V, V
GS
= 0 V,
f = 1.0 MHz
DYNAMIC CHARACTERISTICS
190
120
40
7
15
14
3
7.1
1.2
1.9
15
30
28
6
10
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
10
4
4.3
S
o
30
1
10
100
-100
1
0.7
1.6
1.2
0.072
0.107
0.116
3
2
0.1
0.18
0.15
V
µA
µA
nA
nA
V
ON CHARACTERISTICS
(Note 2)
Ω
A
SWITCHING CHARACTERISTICS
(Note 2)
NDS8961 Rev.D
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
I
S
V
SD
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Parameter
Conditions
Min
Typ
Max
1.3
Units
A
V
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 1.3 A
(Note 2)
0.79
1.2
P
D
(
t
) =
R
θ
JA
(
t
)
T
J
−
T
A
=
T
J
−
T
A
R
θ
JC
+
R
θ
CA
(
t
)
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 78
o
C/W when mounted on a 0.5 in
2
pad of 2oz copper.
b. 125
o
C/W when mounted on a 0.02 in
2
pad of 2oz copper.
c. 135
o
C/W when mounted on a 0.003 in
2
pad of 2oz copper.
1a
1b
1c
Scale 1 : 1 on letter size paper.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS8961 Rev.D
Typical Electrical Characteristics
10
V
GS
=10V
I
D
, DRAIN-SOURCE CURRENT (A)
8
6.0
2.5
5.0
4.5
4.0
R
DS(on)
, NORMALIZED
V
GS
= 3.5V
DRAIN-SOURCE ON-RESISTANCE
2
4.0
4.5
6
1.5
5.0
5.5
6.0
7.0
4
3.5
8.0
2
1
10
3.0
0
0
0.5
1
1.5
2
V
DS
, DRAIN-SOURCE VOLTAGE (V)
2.5
3
0.5
0
2
4
6
I
D
, DRAIN CURRENT (A)
8
10
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Gate
Voltage and Drain Current.
1 .8
2.5
I
D
= 3.1A
DRAIN-SOURCE ON-RESISTANCE
DRAIN-SOURCE ON-RESISTANCE
1 .6
V
2
GS
= 10V
V
GS
= 10V
R
DS(on)
, NORMALIZED
R
DS(ON)
, NORMALIZED
1 .4
1.5
T = 125°C
J
25°C
1 .2
1
1
0 .8
0.5
-55°C
0 .6
-50
-25
0
J
25
50
75
100
125
150
0
0
2
I
D
T , JUNCTION TEMPERATURE (°C)
4
6
, DRAIN CURRENT (A)
8
10
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
10
8
I , DRAIN CURRENT (A)
25°C
125°C
V
th
, NORMALIZED
GATE-SOURCE THRESHOLD VOLTAGE
V
DS
= 10V
T = -55°C
J
1.2
V
DS
= V
GS
1.1
I
D
= 250µA
1
6
0.9
4
0.8
D
2
0.7
0
1
2
V
GS
3
4
5
, GATE TO SOURCE VOLTAGE (V)
6
0.6
-50
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
J
125
150
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation with
Temperature.
NDS8961 Rev.D
Typical Electrical Characteristics
1.12
DRAIN-SOURCE BREAKDOWN VOLTAGE
10
5
I
D
= 250µA
I , REVERSE DRAIN CURRENT (A)
1.08
V
GS
=0V
1
BV
DSS
, NORMALIZED
TJ = 125°C
0 .1
1.04
25°C
0 .0 1
1
-55°C
0.96
0 .0 0 1
0.92
-50
S
-25
0
T
J
25
50
75
100
, JUNCTION TEMPERATURE (°C)
125
150
0 .0 0 0 1
0
0 .2
V
SD
0 .4
0.6
0 .8
1
, BODY DIODE FORWARD VOLTAGE (V)
1 .2
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage Variation
with Current and Temperature
.
600
400
, GATE-SOURCE VOLTAGE (V)
10
I
D
= 3.1A
8
V
DS
= 5V
10V
15V
CAPACITANCE (pF)
200
Ciss
Coss
6
100
70
50
30
20
0 .1
4
f = 1 MHz
V
GS
= 0 V
0 .2
V
0 .5
1
2
5
10
, DRAIN TO SOURCE VOLTAGE (V)
Crss
V
20
30
0
0
GS
2
2
Q
g
4
, GATE CHARGE (nC)
6
8
DS
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
V
DD
V
IN
D
t
on
t
off
t
r
90%
R
L
V
OUT
DUT
t
d(on)
t
d(off)
90%
t
f
V
GS
V
OUT
R
GEN
10%
10%
INVERTED
G
90%
S
V
IN
10%
50%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms
.
NDS8961 Rev.D
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