MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder
September 1983
Revised February 1999
MM74HC259
8-Bit Addressable Latch/3-to-8 Line Decoder
General Description
The MM74HC259 device utilizes advanced silicon-gate
CMOS technology to implement an 8-bit addressable latch,
designed for general purpose storage applications in digital
systems.
The MM74HC259 has a single data input (D), 8 latch out-
puts (Q1–Q8), 3 address inputs (A, B, and C), a common
enable input (G), and a common CLEAR input. To operate
this device as an addressable latch, data is held on the D
input, and the address of the latch into which the data is to
be entered is held on the A, B, and C inputs. When
ENABLE is taken LOW the data flows through to the
addressed output. The data is stored when ENABLE transi-
tions from LOW-to-HIGH. All unaddressed latches will
remain unaffected. With enable in the HIGH state the
device is deselected, and all latches remain in their previ-
ous state, unaffected by changes on the data or address
inputs. To eliminate the possibility of entering erroneous
data into the latches, the enable should be held HIGH
(inactive) while the address lines are changing.
If enable is held HIGH and CLEAR is taken LOW all eight
latches are cleared to a LOW state. If enable is LOW all
latches except the addressed latch will be cleared. The
addressed latch will instead follow the D input, effectively
implementing a 3-to-8 line decoder.
All inputs are protected from damage due to static dis-
charge by diodes to V
CC
and ground.
Features
s
Typical propagation delay: 18 ns
s
Wide supply range: 2–6V
s
Low input current: 1
µA
maximum
s
Low quiescent current: 80
µA
maximum (74HC Series)
Ordering Code:
Order Number
MM74HC259M
MM74HC259SJ
MM74HC259MTC
MM74HC259N
Package Number Package Description
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Latch Selection Table
Select Inputs
C
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Latch
Addressed
0
1
2
3
4
5
6
7
Top View
H
=
HIGH level, L
=
LOW level
D
=
the level at the data input
Q
i0
the level of Q
i
(i
=
0, 1 ...7, as appropriate)
before the indicated steady-state input
conditions were established.
© 1999 Fairchild Semiconductor Corporation
DS005006.prf
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MM74HC259
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260°C
600 mW
500 mW
−0.5
to
+7.0V
−1.5
to V
CC
+1.5V
−0.5
to V
CC
+0.5V
±20
mA
±25
mA
±50
mA
−65°C
to
+150°C
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
) V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
1000
500
400
ns
ns
ns
−40
+85
°C
2
0
Max
6
V
CC
Units
V
V
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
−
12 mW/°C from 65°C to 85°C
DC Electrical Characteristics
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
Conditions
(Note 4)
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0
4.5
6.0
4.2
5.7
0
0
0
0.2
0.2
T
A
=
25°C
Typ
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±0.1
8.0
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1.0
80
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1.0
160
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
V
OL
Maximum LOW Level
Output Voltage
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
20
µA
2.0V
4.5V
6.0V
V
IN
=
V
IH
or V
IL
|I
OUT
|
≤
4.0 mA
|I
OUT
|
≤
5.2 mA
I
IN
I
CC
Maximum Input
Current
Maximum Quiescent
Supply Current
V
IN
=
V
CC
or GND
I
OUT
=
0
µA
6.0V
V
IN
=
V
CC
or GND
4.5V
6.0V
6.0V
4.5V
6.0V
Note 4:
For a power supply of 5V
±10%
the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=5.5V
and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage current
(I
IN
, I
CC
, and I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
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MM74HC259
AC Electrical Characteristics
(V
CC
=
5.0V, T
A
=
25
°
C, t
r
=
t
f
=
6 ns, C
L
=
15 pF unless otherwise specified.)
Symbol
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
t
W
t
W
t
r
, t
f
t
s
t
H
Parameter
Maximum Propagation Delay
Data to Output
Maximum Propagation Delay
Select to Output
Maximum Propagation Delay
Enable to Output
Maximum Propagation Delay
Clear to Output
Minimum Enable Pulse Width
Minimum Clear Pulse Width
Maximum Input Rise and Fall Time
Minimum Setup Time Select or
Data to Enable
Minimum Hold Time Data or
Address to Enable
−2
0
ns
15
10
10
16
16
500
20
ns
ns
ns
ns
17
27
ns
20
35
ns
20
38
ns
Conditions
Typ
18
Guaranteed
Limit
32
Units
ns
AC Electrical Characteristics
t
r
=
t
f
=
6 ns, C
L
=
50 pF, V
CC
=
2.0V – 6.0V
Symbol
Parameter
Conditions
V
CC
2.0V
4.5V
6.0V
t
PHL
, t
PLH
Maximum Propagation Delay
Select to Output
t
PHL
, t
PLH
Maximum Propagation Delay
Enable to Output
t
PHL
Maximum Propagation Delay
Clear to Output
t
W
Minimum Pulse Width
Clear or Enable
t
s
Minimum Setup Time Address
or Data to Enable
t
H
Minimum Hold Time Address
or Data to Enable
t
TLH
, t
THL
Maximum Output Rise
and Fall Time
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (Note 5)
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
=
C
PD
V
CC2
f
+
I
CC
V
CC
, and the no load dynamic current consumption,
I
S
=
C
PD
s V
CC
sf
+
I
CC
.
T
A
=
25°C
Typ
60
19
17
72
21
18
65
27
23
50
18
16
180
37
32
220
43
37
200
40
35
150
31
26
80
16
14
100
20
15
−10
−2
−2
30
8
7
5
80
0
0
0
75
15
13
10
T
A
= −40
to 85°C T
A
= −55
to 125°C
Guaranteed Limits
225
46
40
275
54
46
250
50
44
190
39
32
100
20
18
125
25
19
0
0
0
95
19
16
10
250
52
45
310
60
52
280
58
50
210
44
37
120
24
20
150
28
25
0
0
0
110
22
19
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
t
PHL
, t
PLH
Maximum Propagation Delay
Data to Output
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
(per package)
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