March 2001
SI3442DV
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is tailored to minimize on-state resistance. These
devices are particularly suited for low voltage applications in
notebook computers, portable phones, PCMICA cards, and
other battery powered circuits where fast switching, and low
in-line power loss are needed in a very small outline surface
mount package.
Features
4.1 A, 20 V. R
DS(ON)
= 0.06
Ω
@ V
GS
= 4.5 V
R
DS(ON)
= 0.075
Ω
@ V
GS
=2.7 V.
Proprietary SuperSOT
TM
-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
____________________________________________________________________________________________
4
3
5
2
6
1
Absolute Maximum Ratings
T
A
= 25°C unless otherwise note
Symbol Parameter
V
DSS
V
GSS
I
D
P
D
Drain-Source Voltage
Gate-Source Voltage - Continuous
Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
(Note 1a)
SI3442DV
20
8
4.1
15
1.6
1
0.8
-55 to 150
°C
W
V
V
A
T
J
,T
STG
Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
30
°C/W
°C/W
© 2001Fairchild Semiconductor Corporation
SI3442DV Rev. A
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= 250 µA
V
DS
= 16 V, V
GS
= 0 V
T
J
= 55 C
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
V
GS
= 8 V, V
DS
= 0 V
V
GS
= -8 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250 µA
T
J
= 125
o
C
Static Drain-Source On-Resistance
V
GS
= 4.5 V, I
D
= 4.1 A
T
J
= 125
o
C
V
GS
= 2.7 V, I
D
= 3.6 A
I
D(on)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
Forward Transconductance
V
GS
= 4.5 V, V
DS
= 5 V
V
DS
= 4.5 V, I
D
= 4.1 A
V
DS
= 10 V, V
GS
= 0 V,
f = 1.0 MHz
15
12
0.4
0.3
0.7
0.5
0.039
0.06
0.05
o
20
1
10
100
-100
V
µA
µA
nA
nA
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
1
0.8
0.06
0.11
0.075
A
S
V
Ω
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
365
230
95
pF
pF
pF
SWITCHING CHARACTERISTICS
(Note 2)
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 10 V,
I
D
= 4.1 A, V
GS
= 4.5 V
V
DD
= 5 V, I
D
= 1 A,
V
GEN
= 4.5 V, R
GEN
= 6
Ω
9
25
28
8
10
1
3.3
17
45
50
15
14
ns
ns
ns
ns
nC
nC
nC
SI3442DV Rev.A
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS
I
S
V
SD
Continuous Source Diode Current
Drain-Source Diode Forward Voltage
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
1.3
V
GS
= 0 V, I
S
= 1.3 A
(Note 2)
0.75
1.2
A
V
P
D
(
t
) =
R
θ
J A
t
)
(
T
J
−
T
A
=
R
θ
J C
R
θ
CA
t
)
+
(
T
J
−
T
A
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 78
o
C/W when mounted on a 1 in
2
pad of 2oz copper.
b. 125
o
C/W when mounted on a 0.01 in
2
pad of 2oz copper.
c. 156
o
C/W when mounted on a 0.003 in
2
pad of 2oz copper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
SI3442DV Rev.A
Typical Electrical Characteristics
15
, DRAIN-SOURCE CURRENT (A)
2.5
DRAIN-SOURCE ON-RESISTANCE
2.0V
9
R
DS(on)
, NORMALIZED
12
V
GS
= 4.5V
3.0V
2.7V
2.5V
2
V
GS
=2.0V
1.5
2.5V
6
2.7V
3.0V
3.5V
3
1.5V
1
4.5V
I
D
0
0
V
DS
0.5
1
2
3
, DRAIN-SOURCE VOLTAGE (V)
0
3
I
D
6
9
12
15
, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics
.
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage
.
1.8
DRAIN-SOURCE ON-RESISTANCE
DRAIN-SOURCE ON-RESISTANCE
2.5
I
D
= 4.1A
1.6
1.4
1.2
1
0.8
0.6
-50
R
DS(ON)
, NORMALIZED
V
GS
= 4.5V
R
DS(on)
, NORMALIZED
V
GS
= 4.5V
2
T = 125°C
J
1.5
25°C
1
0.5
-55°C
-25
0
J
25
50
75
100
125
150
0
0
3
6
9
12
15
T , JUNCTION TEMPERATURE (°C)
I
D
, DRAIN CURRENT (A)
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation
with Drain Current and Temperature
.
15
GATE-SOURCE THRESHOLD VOLTAGE
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-50
-25
0
J
V
DS
=- 5V
I , DRAIN CURRENT (A)
12
25°C
TJ = -55°C
125°C
V
th
, NORMALIZED
V
DS
= V
GS
I
D
= 250µA
9
6
D
3
0
0
0.5
V
GS
1
1.5
2
2.5
3
25
50
75
100
125
150
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE (°C)
Figure 5. Transfer Characteristics
.
Figure 6. Gate Threshold Variation
with Temperature
.
SI3442DV Rev.A
Typical Electrical Characteristics
(continued)
DRAIN-SOURCE BREAKDOWN VOLTAGE
1.12
I
S
, REVERSE DRAIN CURRENT (A)
10
5
1
I
D
= 250µA
1.08
V
GS
=0V
TJ = 125°C
BV
DSS
, NORMALIZED
1.04
0.1
25°C
-55°C
1
0.01
0.96
0.001
0.92
-50
-25
T
0
J
25
50
75
100
125
150
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
, JUNCTION TEMPERATURE (°C)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature
.
1500
1000
CAPACITANCE (pF)
600
5
V
GS
, GATE-SOURCE VOLTAGE (V)
V
DS
= 5V
I
D
= 4.1A
10V
15V
4
Ciss
300
200
3
Coss
f = 1 MHz
V
GS
= 0V
2
100
Crss
1
50
0.1
0
0.2
V
DS
0.5
1
2
5
10
20
0
3
6
Q
g
, GATE CHARGE (nC)
9
12
, DRAIN TO SOURCE VOLTAGE (V)
Figure 9. Capacitance Characteristics
.
Figure 10. Gate Charge Characteristics.
V
DD
t
d(on)
t
on
t
off
t
r
90%
t
d(off)
90%
t
f
V
IN
D
R
L
V
OUT
V
OUT
10%
V
GS
R
GEN
10%
INVERTED
G
DUT
90%
S
V
IN
10%
50%
50%
PULSE WIDTH
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms
.
SI3442DV Rev.A
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
