NCP3133A
3 A Integrated Synchronous
Buck Converter
NCP3133A is a fully integrated synchronous buck converter for
3.3 V and 5 V step−down applications. It can provide up to 3 A load
current. NCP3133A supports high efficiency, fast transient response
and provides power good indicator. The control scheme includes two
operation modes: FCCM and automatic CCM/DCM. In automatic
CCM/DCM mode, the controller can smoothly switch between CCM
and DCM, where converter runs at reduced switching frequency with
much higher efficiency. NCP3133A is available in 3 mm x 3 mm
QFN−16 pin package.
Features
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QFN16 3 x 3, 0.5P
CASE 485DA
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High Efficiency in both CCM and DCM
High Operation Frequency at 1.1 MHz
Support MLCC Output Capacitor
Small Footprint, 3 mm x 3 mm, 16−pin QFN Package
Up to 3 A Continuous Output Current
2.9 V to 5.5 V Wide Conversion Voltage Range
Output Voltage Range from 0.6 V to 0.84 X Vin
Internal 400
ms
Soft−Start
Automatic Power−Saving Mode
Voltage Mode Control
Support Pre-bias Start−up Functionality
Output Discharge Operation
Over−Temperature Protection
Built−in Over−Voltage, Under−Voltage and Over-Current Protection
Power Good Indicator
This is a Pb−Free Device
SUGGESTED PIN ARRANGEMENT
PGND PGND VIN VIN
16
EN
NC
PGD
VBST
1
2
NCP3133A
3
4
5
SW
6
SW
7
SW
8
PS
10 FB
9
COMP
15
14
13
12 VDD
11 AGND
MARKING DIAGRAM
3133A
ALYWG
G
3133A
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Applications
•
5 V Step Down Rail
•
3.3 V Step Down Rail
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 12 of this data sheet.
©
Semiconductor Components Industries, LLC, 2016
1
April, 2016 − Rev. 2
Publication Order Number:
NCP3133A/D
NCP3133A
VIN
VBST
UVLO
NC
OSC
Ramp
PS
EN
COMP
VREF
FB
PGD
+
+ E/A
−
Control Logic
&
PWM Logic
DRVH
SW
SS
DRVL
Power Good,
UVP, OVP, UVLO,
Overtemperature
and Vout discharge
PGND
OCP
UVLO
VDD
AGND
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin No.
1
2
3
4
5, 6, 7
8
Symbol
EN
NC
PGD
VBST
SW
PS
Description
Logic control to enabling the switcher. Internally pulled up to VDD with a 1.35 MW resistor
Not connected
Open drain power good output
Gate drive voltage for high side FET. Connect capacitor from this pin to SW
Switch node between high−side MOSFET and low−side MOSFET
Mode configuration pin (with 10
mA
current):
Pulled high or floating (internally pulled high): Forced Continuous Conduction Mode
Connect with resistor equal to or lower than (≤)174 kW to GND: Automatic CCM/DCM
Output of the error amplifier
Feedback pin. Connect to resistor divider to set up the desired output voltage
Analog ground
Power supply input for control circuitry
Power input for power conversion and gate driver supply
Power ground
9
10
11
12
13, 14
15, 16
COMP
FB
AGND
VDD
VIN
PGND
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NCP3133A
Vin = 2.9 V
X
5.5 V
L1
C5
C6
R6
13
VIN
12 VDD
11 AGND
14
VIN
5
6
7
SW SW SW
VBST 4
C4
Vin
R7
C7
C9
C8
NCP3133A
2 NC
EN
R5
8 PS
PGND
15
PGND
16
COMP 9
R2
C3
1 EN
PGD 3
FB 10
C2
R4
R1
PGD
R3
C1
Vout
Figure 2. NCP3133A Single Voltage Rail for V
IN
and V
DD
L1
Vin = 2.9 V
X
5.5 V
C5
C6
13
VIN
12 VDD
11 AGND
14
VIN
5
6
7
SW SW SW
VBST 4
C4
Vin
R7
C7
C9
V
DD
= 3.3 V
C8
NCP3133A
2 NC
EN
R5
8 PS
PGND
15
PGND
16
COMP 9
R2
C3
1 EN
PGD 3
FB 10
C2
R4
R1
PGD
R3
C1
Vout
Figure 3. NCP3133A Dual Voltage Rail for V
IN
and V
DD
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NCP3133A
Table 2. ABSOLUTE MAXIMUM RATINGS
Value
Rating
Input Voltage Range
VIN, VDD
VBST
VBST (with respect to SW)
FB, PS, EN
Output Voltage Range
SW
DC
Pulse < 20 ns, E = 5
mJ
PGD
COMP
PGND
Operation ambient temperature
Storage temperature
Junction temperature
Electrostatic Discharge
T
A
T
S
T
J
Human Body Model (HBM)
Charged Device Model (CDM)
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds
Symbol
Min
−0.3
−0.3
−0.3
−0.3
−1
−3
−0.3
−0.3
−0.3
−40
−55
−40
2000
500
300
°C
Max
6.5
17
7
VDD+0.3V
7
10
7
3.7
0.3
85
150
150
V
°C
V
Units
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. RECOMMENDED OPERATION RATINGS
Value
Rating
Input Voltage Range
VIN
VDD
VBST
VBST (with respect to SW)
EN
FB, PS
Output Voltage Range
SW
PGD
COMP
PGND
Junction temperature range, T
J
Symbol
Min
2.9
2.9
−0.1
−0.1
−0.1
−0.1
−1
−0.1
−0.1
−0.1
−40
Nom
Max
5.5
5.5
13.5
6
VDD
VDD
6.5
6
3.5
0.1
125
°C
V
Units
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 4. THERMAL INFORMATION
Rating
Junction−to−Ambient Thermal Resistance (Note 1)
1. The maximum package power dissipation limit must not be exceeded.
Value
45
Units
°C/W
P
D
+
T
J(MAX)
*
T
A
R
qJA
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NCP3133A
Table 5. ELECTRICAL CHARACTERISTICS
(V
DD
= V
IN
= 3.3 V and V
DD
= V
IN
= 5.0 V, over recommended free air temperature range, PGND = GND unless otherwise noted)
Parameter
POWER SUPPLY
VIN operation voltage
VIN UVLO threshold
VIN UVLO hysteresis
VDD internal bias voltage
VDD UVLO threshold
VDD UVLO hysteresis
VOLTAGE MONITOR
Power good low voltage
Power good high leakage current
Power good threshold
Feedback lower voltage limit
Feedback higher voltage limit
Power good high delay
Minimum Vin voltage for valid PGD
at start up
Output over-voltage protection
threshold at FB
Over-voltage blanking time
Output under-voltage protection
threshold at FB
Under-voltage blanking time
SUPPLY CURRENT (T
J
= +255C)
VDD quiescent current
VDD shutdown supply current
Vin shutdown supply current
I
VDD
I
VDD_SD
I
QSHDN
EN = ‘HI’, no switching
EN = ‘LO’
EN = ‘LO’
2.2
3.5
8.0
3.5
mA
mA
mA
T
UVPDLY
Time from FB lower than 20% of Vref to
UVP fault
T
OVPDLY
Time from FB higher than 20% of Vref to
OVP fault
t
PGDELAY
Measured at Vin with 1 mA (or 2 mA) sink
current on PGD pin at start up
114
1.0
80
Pull−down voltage with 4 mA sink current
−2.0
80
114
200
0
83
117
400
1
117
1.7
83
11
120
2.5
86
400
2.0
86
120
mV
mA
%Vref
%Vref
ms
V
%Vref
ms
%Vref
ms
Nominal 3.3 V input voltage range
Ramp up; EN = ‘HI’
2.9
2.8
75
V
IN
Nominal input voltage range
Ramp up; EN = ‘HI’
2.9
2.8
130
5.5
5.5
V
V
mV
V
V
mV
Symbol
Test Conditions
Min
Typ
Max
Units
FEEDBACK VOLTAGE & ERROR AMPLIFIER
Reference voltage at FB
Unity gain bandwidth (Note 1)
Open loop gain (Note 1)
FB pin leakage current
Output sourcing and sinking current
(Note 1)
Slew rate (Note 1)
OVER CURRENT PROTECTION & ZERO CROSSING
Over-current limit on high−side FET
When Iout exceeds this threshold for 4
consecutive cycles. Vin = 3.3 V, Vout =
1.5 V with 1
mH
inductor, T
A
= +25°C
Immediately shut down when sensed cur-
rent reach this value. Vin = 3.3 V, Vout =
1.5 V with 1
mH
inductor, T
A
= +25°C
PGND−SWN, Automatic CCM/DCM mode
4.2
4.8
5.4
A
Ccomp = 20 pF
5
5
V
REF
0°C < T
A
< 85°C
−40°C < T
A
< 85°C
594
592.5
14
80
100
600
600
606
607.5
mV
MHz
dB
nA
mA
V/
ms
One time over-current latch off on
the low−side FET
Zero crossing comparator internal
offset (Note 1)
4.8
5.4
A
−4.5
−3.0
−1.5
mV
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