HIGH-SPEED
4K x 16 DUAL-PORT
STATIC RAM
Features
◆
◆
◆
IDT7024S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7024S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7024L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT7024 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for
BUSY
output flag on Master
M/S = L for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin
Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts availble, see ordering information
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
Functional Block Diagram
R/W
L
UB
L
R/W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
BUSY
L
A
11L
A
0L
(1,2)
I/O
8R
-I/O
15R
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
R
Address
Decoder
12
(1,2)
MEMORY
ARRAY
12
Address
Decoder
A
11R
A
0R
CE
L
OE
L
R/W
L
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(2)
2740 drw 01
M/S
MAY 2018
1
©2018 Integrated Device Technology, Inc.
DSC 2740/12
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7024 is a high-speed 4Kx 16 Dual-Port Static RAM. The
IDT7024 is designed to be used as a stand-alone 64K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 32-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by chip enable (CE) permits the on-chip circuitry of each
port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power. Low-power (L)
versions offer battery backup data retention capability with typical power
consumption of 500µW from a 2V battery.
The IDT7024 is packaged in a ceramic 84-pin PGA, an 84-pin Flatpack
and PLCC, and a 100-pin TQFP. Military grade product is manufactured
in compliance with the latest revision of MIL-PRF-38535 QML, making it
ideally suited to military temperature applications demanding the highest
level of performance and reliability.
Pin Configurations
(1,2,3)
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
I/O
1L
I/O
0L
GND
R/W
L
SEM
L
A
11L
OE
L
V
CC
CE
L
UB
L
LB
L
N/C
A
10L
A
9L
INDEX
A
8L
11/06/01
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
I/O
8L
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
11 10 9 8 7 6 5 4
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
3 2 1 84 83 82 81 80 79 78 77 76 75
74
73
72
71
70
69
IDT7024J or F
J84-1
(4)
F84-2
(4)
68
67
66
65
64
63
62
61
60
59
58
57
56
55
84-Pin PLCC / Flatpack
Top View
(5)
N/C
A
11R
I/O
14R
GND
A
10R
I/O
9L
I/O
8L
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
OE
L
V
CC
R/W
L
SEM
L
CE
L
UB
L
LB
L
N/C
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
68
67
66
54
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
I/O
10R
I/O
11R
I/O
12R
I/O
15R
OE
R
R/W
R
I/O
13R
I/O
9R
GND
A
9R
A
8R
SEM
R
CE
R
UB
R
LB
R
A
7R
Index
,
2740 drw 02
N/C
N/C
N/C
N/C
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
N/C
N/C
N/C
N/C
11/06/01
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
N/C
N/C
N/C
N/C
IDT7024PF
PN100-1(4)
100-Pin TQFP
Top View(5)
65
64
63
62
61
60
59
58
57
56
55
54
53
52
NOTES:
1. All V
CC
pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.
F84-2 package body is approximately 1.17 in x 1.17 in x .11 in.
PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
,
6.42
2
I/O
7R
I/O
8R
I/O
9R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
GND
I/O
15R
OE
R
R/W
R
GND
SEM
R
CE
R
UB
R
LB
R
N/C
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
2740 drw 03
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
63
61
60
58
55
54
51
48
46
45
42
11
I/O
7L
66
I/O
5L
64
I/O
4L
62
I/O
2L
59
I/O
0L
56
OE
L
49
SEM
L
50
LB
L
47
A
11L
44
A
10L
43
A
7L
40
10
I/O
10L
67
I/O
8L
65
I/O
6L
I/O
3L
I/O
1L
57
UB
L
53
CE
L
52
N/C
A
9L
A
8L
41
A
5L
39
09
I/O
11L
69
I/O
9L
68
GND
V
CC
R/W
L
A
6L
38
A
4L
37
08
I/O
13L
72
I/O
12L
71
73
33
A
3L
35
A
2L
34
07
I/O
15L
75
I/O
14L
70
V
CC
74
BUSY
L
IDT7024G
G84(4)
84-Pin PGA
Top View(5)
32
A
0L
31
INT
L
36
06
I/O
0R
76
GND
77
GND
78
GND
28
M/S
29
A
1L
30
05
I/O
1R
79
I/O
2R
80
V
CC
A
0R
INT
R
26
BUSY
R
27
04
I/O
3R
81
I/O
4R
83
7
11
12
A
2R
23
A
1R
25
03
I/O
5R
82
1
I/O
7R
2
5
GND
8
GND
10
SEM
R
14
17
20
A
5R
22
A
3R
24
02
I/O
6R
84
3
I/O
9R
I/O
10R
4
I/O
13R
6
I/O
15R
9
R/W
R
15
UB
R
13
A
11R
16
A
8R
18
A
6R
19
A
4R
21
01
I/O
8R
A
I/O
11R
B
I/O
12R
C
I/O
14R
D
OE
R
E
LB
R
F
CE
R
G
N/C
H
A
10R
J
A
9R
K
A
7R
L
2740 drw 04
,
Index
NOTES:
1. All V
CC
pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. Package body is approximately 1.12 in x 1.12 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
11L
I/O
0L
- I/O
15L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
- A
11R
I/O
0R
- I/O
15R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
M/S
V
CC
GND
Right Port
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2740 tbl 01
Names
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Military
Commercial
Industrial
Ambient
Temperature
-55
O
C to +125
O
C
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
5.0V
+
10%
2740 tbl 02
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
6.42
3
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
CE
H
X
L
L
L
L
L
L
X
R/W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
I/O
8-15
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
Outputs
I/O
0-7
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Deselcted: Power-Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
2740 tbl 03
Mode
NOTE:
1. A
0L
— A
11L
≠
A
0R
— A
11R
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
(1)
CE
(2)
H
X
H
X
L
L
R/W
H
H
↑
↑
X
X
OE
L
L
X
X
X
X
UB
X
H
X
H
L
X
LB
X
H
X
H
X
L
SEM
L
L
L
L
L
L
I/O
8-15
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
____
____
Outputs
I/O
0-7
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
____
____
Mode
Read Semaphore Flag Data Out
Read Semaphore Flag Data Out
Write I/O
0
into Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
Not Allowed
2740 tbl 04
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all of the I/O's (I/O
0
- I/O
15
).
These eight semaphores are addressed by A
0
- A
2
.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Military
-0.5 to +7.0
Unit
V
Recommended DC Operating
Conditions
Symbol
V
CC
GND
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
2740 tbl 06
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
o
C
C
V
IH
V
IL
o
mA
2740 tbl 05
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. V
TERM
must not exceed Vcc +10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period over V
TERM
>
Vcc + 10%
.
6.42
4
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Capacitance
(T
A
= +25°C, f = 1.0MHz)
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
2740 tbl 07
NOTES:
1. This parameter are determined by device characterization, but is not
production tested.
2. 3dV references the interpolated capacitance when the input and
output signals switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 5.0V ± 10%)
7024S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
7024L
Max.
10
10
0.4
___
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
2740 tbl 08
2.4
2.4
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
(V
CC
= 5.0V ± 10%)
7024X15
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Test Condition
CE
= V
IL
,
Outputs Disabled
SEM
= V
IH
f = f
MAX
(3)
CE
R
=
CE
L
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX
(3)
Version
COM'L
MIL &
IND
COM'L
MIL &
IND
COM'L
MIL &
IND
COM'L
MIL &
IND
COM'L
MIL &
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
Typ.
(2)
170
170
____
____
7024X17
Com'l Only
Typ.
(2)
170
170
____
____
7024X20
Com'l, Ind
& Military
Typ.
(2)
160
160
160
160
20
20
20
20
95
95
95
95
1.0
0.2
1.0
0.2
90
90
90
90
Max.
290
240
370
320
60
50
90
70
180
150
240
210
15
5
30
10
155
130
225
200
7024X25
Com'l &
Military
Typ.
(2)
155
155
155
155
16
16
16
16
90
90
90
90
1.0
0.2
1.0
0.2
85
85
85
85
Max.
265
220
340
280
60
50
80
65
170
140
215
180
15
5
30
10
145
120
200
170
2740 tbl 09a
Max.
310
260
____
____
Max.
310
260
____
____
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
20
20
____
____
60
50
____
____
20
20
____
____
60
50
____
____
mA
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
SEM
R
=
SEM
L
= V
IH
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
=
SEM
L
> V
CC
- 0.2V
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
=
SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(3)
105
105
____
____
190
160
____
____
105
105
____
____
190
160
____
____
mA
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
1.0
0.2
____
____
15
5
____
____
1.0
0.2
____
____
15
5
____
____
mA
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
100
100
____
____
170
140
____
____
100
100
____
____
170
140
____
____
mA
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. V
CC
= 5V, T
A
= +25°C, and are not production tested. I
CC DC
= 120mA (TYP.)
3. At f = f
MAX
,
address and I/O'
S
are cycling at the maximum frequency read cycle of 1/t
RC
, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.42
5
FPGA/CPLD
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