Programmable Low Additive Jitter 2:8
Buffer with Dividers and Universal Outputs
8P79818
Datasheet
Description
The device is intended to take 1 or 2 reference clocks, select
between them, using a pin or register selection and generate up to 8
outputs that may be the same as the reference frequency or
integer-divider versions of it.
The 8P79818 supports two output banks, each with its own divider
and power supply. All outputs in one bank would generate the same
output frequency, but each output can be individually controlled for
output type, output enable or even powered-off.
The device supports a serial port for configuration of the parameters
while in operation. The serial port can be selected to use the I
2
C or
SPI protocol. After power-up, all outputs will come up in LVDS mode
and may be programmed to other configurations over the serial port.
Outputs may be enabled or disabled under control of the OE input
pin.
The device can operate over the -40°C to +85°C temperature range.
Features
▪
Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS
reference clocks
— Accepts input frequencies ranging from 1PPS (1Hz) to
700MHz
▪
Select which of the two input clocks is to be used as the reference
clock for which divider via pin or register selection
— Switchover will not generate any runt clock pulses on the
output
▪
Generates eight differential outputs
or eight LVCMOS outputs, Bank A only
— Differential outputs selectable as LVPECL, LVDS, CML or
HCSL
— Differential outputs support frequencies from 1PPS to 700MHz
— LVCMOS outputs support frequencies from 1PPS to 200MHz
— LVCMOS outputs in the same pair may be inverted or in-phase
relative to one another
▪
Outputs arranged in 2 banks of 4 outputs each
— Each bank supports a separate power supply of 3.3V, 2.5V or
1.8V
— 1.5V output voltage is also supported for LVCMOS, Bank A
only
— One divider per output bank, supporting divide ratios of 2...511
or divider bypass
▪
Output enable control pin
— Output enable or disable will not cause any runt pulses
▪
Register programmable via I
2
C / SPI serial port
— Individual output enables, output type selection and output
power-down control bits supported
— Input mux selection control bit
▪
Core voltage supply of 3.3V, 2.5V or 1.8V
▪
-40°C to +85°C ambient operating temperature
▪
Lead-free (RoHS 6) packaging
©2016 Integrated Device Technology, Inc.
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8P79818 Datasheet
Block Diagram
Figure 1: Block Diagram
Bank A
DIV A
(2 to 511)
QA0
nQA0
QA1
nQA1
CLK_SEL
CLK0
nCLK0
PU/PD
PU
QA2
Div‐by‐1
PD
nQA2
QA3
nQA3
Bank B
CLK1
nCLK1
PU/PD
OE
PU
PD
DIV B
(2 to 511)
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
SCLK
PU
Div‐by‐1
SDATA/SDI PU
SA0/nCS PU
Logic
nI2C/SPI
PD
8P79818 transistor count: 33,394
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December 19, 2016
8P79818 Datasheet
Pin Assignment
Figure 2: Pin Assignments for 5mm x 5mm 32-Lead VFQFN Package (Top View)
SDATA/SDI
nCLK0
nCLK1
26
SCLK
CLK0
32
31
30
29
28
27
SDO
QA0
nQA0
QA1
nQA1
V
CCOA
QA2
nQA2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK1
25
24
23
22
V
CC
V
CC
CLK_SEL
QB0
nQB0
QB1
nQB1
V
CCOB
8P79818
21
20
19
18
17
QB2
nQB2
nI2C/SPI
V
CC
SA0/nCS
nQA3
nQB3
QA3
Pin Description and Characteristic Tables
Table 1: Pin Description
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
Name
SDO
QA0
nQA0
QA1
nQA1
V
CCOA
QA2
nQA2
QA3
nQA3
nI2C/SPI
V
CC
SA0/nCS
Type
[a]
Output
Output
Output
Output
Output
Power
Output
Output
Output
Output
Input (PD)
Power
Input (PU)
QB3
OE
Description
SPI mode data output signal. Unused in I
2
C mode.
Positive differential clock output. Included in Bank A. Refer to
Output Drivers
section for details.
Negative differential clock output. Included in Bank A. Refer to
Output Drivers
section for details.
Positive differential clock output. Included in Bank A. Refer to
Output Drivers
section for details.
Negative differential clock output. Included in Bank A. Refer to
Output Drivers
section for details.
Output supply for output Bank A.
Positive differential clock output. Included in Bank A. Refer to
Output Drivers
section for details.
Negative differential clock output. Included in Bank A. Refer to
Output Drivers
section for details.
Positive differential clock output. Included in Bank A. Refer to
Output Drivers
section for details.
Negative differential clock output. Included in Bank A. Refer to
Output Drivers
section for details.
Select protocol for serial port:
0 = I
2
C mode
1 = SPI mode
Core logic supply.
SPI chip select input (active low) in SPI mode. Base address bit 0 in I
2
C mode.
©2016 Integrated Device Technology, Inc.
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8P79818 Datasheet
Table 1: Pin Description (Cont.)
Master output enable control
14
15
16
17
18
19
20
21
22
23
OE
nQB3
QB3
nQB2
QB2
V
CCOB
nQB1
QB1
nQB0
QB0
Input (PU)
Output
Output
Output
Output
Power
Output
Output
Output
Output
0 = All outputs high-impedance
1 = All outputs enabled or disabled under control of register bits
Negative differential clock output. Included in Bank B. Refer to
Output Drivers
section for details.
Positive differential clock output. Included in Bank B. Refer to
Output Drivers
section for details.
Negative differential clock output. Included in Bank B. Refer to
Output Drivers
section for details.
Positive differential clock output. Included in Bank B. Refer to
Output Drivers
section for details.
Output supply for output Bank B.
Negative differential clock output. Included in Bank B. Refer to
Output Drivers
section for details.
Positive differential clock output. Included in Bank B. Refer to
Output Drivers
section for details.
Negative differential clock output. Included in Bank B. Refer to
Output Drivers
section for details.
Positive differential clock output. Included in Bank B. Refer to
Output Drivers
section for details.
Input clock selection control pin. This pin may be disabled by register control, but if enabled
(default) its function is:
0 = CLK0 is selected
1 = CLK1 is selected
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 when left floating (set by the internal pull-up and
pull-down resistors).
Core logic supply.
Serial port input clock for either SPI or I
2
C mode.
In I
2
C mode, this is the bi-directional data signal for the serial port
In SPI mode, this is the data input signal.
Core logic supply.
Inverting differential clock input. V
CC
/2 when left floating (set by the internal pull-up and
pull-down resistors).
Non-inverting differential clock input.
Must be connected to ground (GND).
24
CLK_SEL
Input (PU)
25
26
27
28
29
30
31
32
EP
CLK1
nCLK1
V
CC
SCLK
SDATA/
SDI
V
CC
nCLK0
CLK0
V
EE
Input (PD)
Input (PU/ PD)
Power
Input (PU)
Input/Output
(PU)
Input (PU)
Power
Input (PU/ PD)
Input (PD)
Ground
a. Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses.
Pullup
and
Pulldown
refer to internal input resistors. See
Table 10,
DC Input/ Output Characteristics,
for typical values.
©2016 Integrated Device Technology, Inc.
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December 19, 2016
8P79818 Datasheet
Principles of Operation
Input Selection
The 8P79818 supports two input references: CLK0 and CLK1 that may be driven with differential or single-ended clock signals. Either or both
may be used as the source frequency for either output divider under control of the CLK_SEL input pin or under register control.
The CLK_SEL pin is the default selection mechanism and selects whether both dividers are driven by the CLK0, nCLK0 input (CLK_SEL =
Low) or by the CLK1, nCLK1 input (CLK_SEL = High).
If the user enables register control via the SEL_REG control bit, then there are 4 selection options available as shown in
Table 2.
Table 2: Input Selection Register Control (SEL_REG = 1)
CLK_SEL [1:0]
0
0
1
1
0
1
0
1
Description
Divider A & B both driven from CLK0
Divider A driven from CLK1 &
Divider B driven from CLK0
Divider A driven from CLK0 &
Divider B driven from CLK1
Divider A & B both driven from CLK1
Output Dividers
Each bank of outputs has its own divider. All outputs in the same bank will be driven by that divider and so will all have the same frequency.
Divider A supplies the QA output bank and Divider B supplies the QB output bank. Each divider is capable of being driven by the same or a
different input frequency. Each divider can pass that input frequency directly to the outputs or to divide it by any integer from 2 up to 511.
Output Drivers
The QA[0:3] and QB[0:3] clock outputs are provided with register-controlled output drivers. By selecting the output drive type in the appropriate
register, any of these outputs can support LVCMOS, LVPECL, CML, HCSL or LVDS logic levels.
CML operation supports both a 400mV peak-peak swing and an 800mV peak-peak swing selection.
The operating voltage ranges of each output bank is determined by its independent output power pin (V
CCOA
or V
CCOB
). Output voltage levels
of 1.8V, 2.5V or 3.3V are supported for differential operation and LVCMOS operation. In addition, LVCMOS output operation supports 1.5V
V
CCO
.
A global OE input pin is provided. If the OE pin is negated (Low), then all outputs will be in a high-impedance state. If the OE pin is asserted
(High), then each output will behave as indicated by its individual register enable bit. Using the global OE pin to enable or disable outputs will
not result in any ‘runt’ clock pulses on the outputs.
Each output bank may be enabled or disabled using the SYNC_DISx register bit. Using these bits to enable or disable outputs will not result in
any ‘runt’ clock pulses on the outputs.
Individual outputs within a bank may be enabled or disabled using the DIS_Qxm register bits. These bits however may result in ‘runt’ pulses on
the outputs if the output is otherwise enabled, so it is recommended that the entire bank be disabled via the appropriate SYNC_DISx register
bit while an individual output is being enabled using the DIS_Qxm bit to avoid a possible ‘runt’ pulse on the output. If ‘runt’ pulses are not a
concern, then the DIS_Qxm bits may be used directly.
LVCMOS Operation
When a given output is configured to provide LVCMOS levels, then both the Q and nQ outputs will toggle at the selected output frequency. All
the previously described configuration and control apply equally to both outputs. Frequency, voltage levels and enable / disable status apply to
both the Q and nQ pins.
When configured as LVCMOS, the Q & nQ outputs can be selected to be phase-aligned with each other or inverted relative to one another.
Phase-aligned outputs will have increased simultaneous switching currents which can negatively affect phase noise performance and power
consumption. It is recommended that use of this selection be kept to a minimum.
©2016 Integrated Device Technology, Inc.
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December 19, 2016
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