Low Additive Jitter 2:8 Buffer with
Universal Differential Outputs
8P391208
Datasheet
General Description
8P391208 is intended to take 1 or 2 reference clocks, select
between them, using a pin selection and generate up to 8 outputs
that are the same as the reference frequency.
8P391208 supports two output banks, each with its own power
supply. All outputs in one bank would generate the same output
frequency, and each bank can be individually controlled for output
type or output enable.
The device can operate over the -40°C to +85°C temperature range.
Features
• Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS
reference clocks
• Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz
(up to 1GHz when configured into HCSL output mode at 3.3V)
• Select which of the two input clocks is to be used as the reference
clock for which bank via pin selection
• Generates 8 differential outputs
• Differential outputs selectable as LVPECL, LVDS, CML or HCSL
• CML mode supports two different voltage swings
• Differential outputs support frequencies from 1PPS to 700MHz
(up to 1GHz when configured into HCSL output mode at 3.3V)
• Outputs arranged in 2 banks of 4 outputs each
• Each bank supports a separate power supply of 3.3V, 2.5V or
1.8V
• Controlled by 3-level input pins
• Input mux selection control pin
• Control inputs are 3.3V-tolerant for all core voltages
• Output noise floor of -153dBc/Hz @ 156.25MHz
• Core voltage supply of 3.3V, 2.5V or 1.8V
• -40°C to +85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
©2016 Integrated Device Technology
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September 1, 2016
8P391208 Datasheet
8P391208 Block Diagram
QA0
nQA0
QA1
nQA1
CLK_SEL
QA2
nQA2
QA3
CLK0
nCLK0
CLK1
nCLK1
nQA3
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
IOA
IOB
2
2
Logic
Pin Assignment
Figure 1: 8P391208 Pin Assignment for 5mm x 5mm 32-pin VFQFN Package
nCLK0
nCLK1
26
CLK0
32
31
30
29
28
27
25
24
23
22
21
20
19
18
17
CLK1
IOA0
IOB0
V
CC
V
CC
IOA1
QA0
nQA0
QA1
nQA1
V
CCOA
QA2
nQA2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IOB1
QB0
nQB0
QB1
nQB1
V
CCOB
QB2
nQB2
nc
CLK_SEL
nQA3
QA3
V
CC
nc
nQB3
©2016 Integrated Device Technology
QB3
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September 1, 2016
8P391208 Datasheet
Pin Description and Characteristic Tables
Table 1: Pin Description
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Name
IOA1
QA0
nQA0
QA1
nQA1
V
CCOA
QA2
nQA2
QA3
nQA3
nc
V
CC
CLK_SEL
nc
nQB3
QB3
nQB2
QB2
V
CCOB
nQB1
QB1
Input
Type
[1]
Pullup /
Pulldown
Description
Controls output functions for Bank A. 3-level input.
Positive differential clock output. Included in Bank A.
Refer to
Output Drivers
section for more details.
Negative differential clock output. Included in Bank A.
Refer to
Output Drivers
section for more details.
Positive differential clock output. Included in Bank A.
Refer to
Output Drivers
section for more details.
Negative differential clock output. Included in Bank A.
Refer to
Output Drivers
section for more details.
Output voltage supply for Output Bank A.
Positive differential clock output. Included in Bank A.
Refer to
Output Drivers
section for more details.
Negative differential clock output. Included in Bank A.
Refer to
Output Drivers
section for more details.
Positive differential clock output. Included in Bank A.
Refer to
Output Drivers
section for more details.
Negative differential clock output. Included in Bank A.
Refer to
Output Drivers
section for more details.
Unused. Do not connect.
Core Logic voltage supply.
Pullup /
Pulldown
Input Clock Selection Control pin. 3-level input. This pin’s function is
described in the Input Selection section.
Unused. Do not connect.
Negative differential clock output. Included in Bank B. Refer to
Output Drivers
section for more details.
Positive differential clock output. Included in Bank B. Refer to
Output Drivers
section for more details.
Negative differential clock output. Included in Bank B. Refer to
Output Drivers
section for more details.
Positive differential clock output. Included in Bank B. Refer to
Output Drivers
section for more details.
Output voltage supply for Output Bank B.
Negative differential clock output. Included in Bank B. Refer to
Output Drivers
section for more details.
Positive differential clock output. Included in Bank B. Refer to
Output Drivers
section for more details.
Output
Output
Output
Output
Power
Output
Output
Output
Output
Unused
Power
Input
Unused
Output
Output
Output
Output
Power
Output
Output
©2016 Integrated Device Technology
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September 1, 2016
8P391208 Datasheet
Table 1: Pin Description (Continued)
22
23
24
25
26
27
28
29
30
31
32
EP
nQB0
QB0
IOB1
CLK1
nCLK1
V
CC
IOB0
IOA0
V
CC
nCLK0
CLK0
V
EE
Output
Output
Input
Input
Input
Power
Input
Input
Power
Input
Input
Ground
Pullup /
Pulldown
Pulldown
Pullup /
Pulldown
Pullup /
Pulldown
Pullup /
Pulldown
Pulldown
Pullup /
Pulldown
Negative differential clock output. Included in Bank B.
Refer to
Output Drivers
section for more details.
Positive differential clock output. Included in Bank B.
Refer to
Output Drivers
section for more details.
Controls output functions for Bank B. 3-level input.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 when left floating (set by the internal
pullup and pulldown resistors).
Core Logic voltage supply.
Controls output functions for Bank B. 3-level input.
Controls output functions for Bank A. 3-level input.
Core Logic voltage supply.
Inverting differential clock input. V
CC
/2 when left floating (set by the internal
pullup and pulldown resistors).
Non-inverting differential clock input.
Exposed pad must be connected to GND.
1.
Pullup
and
Pulldown
refer to internal input resistors. See
Table 2,
Pin Characteristics,
for typical values.
Table 2: Pin Characteristics
Symbol
C
IN
Parameter
Input Capacitance
LVPECL
Power Dissipation
Capacitance
(per output pair)
LVDS
CML, 400mV
CML, 800mV
LVPECL
Test Conditions
Minimum
Typical
2
Maximum
Units
pF
pF
pF
pF
pF
pF
pF
pF
pF
k
k
V
CCOx[1]
= 3.465V or 2.625V
2.0
C
PD
QA[0:3], nQA[0:3];
LVDS
QB[0:3], nQB[0:3]
CML, 400mV
CML, 800mV
R
PULLUP
R
PULLDOWN
Input Pullup Resistor
Input Pulldown Resistor
V
CCOx
[1]
= 1.89V
2.5
51
51
1. V
CCOx
refers to V
CCOA
for QA[3:0], nQA[3:0] or V
CCOB
for QB[3:0], nQB[3:0].
©2016 Integrated Device Technology
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September 1, 2016
8P391208 Datasheet
Principles of Operation
Input Selection
The 8P391208 supports two input references: CLK0 and CLK1 that may be driven with differential or single-ended clock signals. Either may be
used as the source frequency for either or both output banks under control of the CLK_SEL input pin.
Table 3: Input Selection Control
CLK_SEL
High
Middle
[1]
Low
Description
Banks A & B Both Driven from CLK1
Bank A Driven from CLK0 & Bank B Driven from CLK1
Banks A & B Both Driven from CLK0
1. A ‘middle’ voltage level is defined in
Table 10.
Leaving the input pin open will
also generate this level via a weak internal resistor network.
Output Drivers
The QA[0:3] and QB[0:3] clock outputs are provided with pin-controlled output drivers. The following table shows how each bank can be
controlled. Each bank is separately controlled and all outputs within a single bank will behave the same way.
Table 4: Output Mode and Enable Control
IOx[1]
High
High
High
Middle
Middle
Middle
Low
Low
Low
IOx[0]
High
Middle
Low
High
Middle
Low
High
Middle
Low
Output Bank Function
All outputs in the bank are high-impedance
All outputs in the bank are LVPECL
All outputs in the bank are LVDS
All outputs in the bank are CML (400mV)
All outputs in the bank are high-impedance
All outputs in the bank are HCSL
All outputs in the bank are CML (800mV)
All outputs in the bank are LVPECL
All outputs in the bank are high-impedance
CML operation supports both a 400mV (pk-pk) swing and an 800mV (pk-pk) swing selection.
The operating voltage ranges of each output is determined by its independent output power pin (V
CCOA
or V
CCOB
) and thus each can have
different output voltage levels. Output voltage levels of 1.8V, 2.5V or 3.3V are supported for differential operation
.
©2016 Integrated Device Technology
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September 1, 2016
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