Crystal oscillator
CRYSTAL OSCILLATOR
PROGRAMMABLE
OUTPUT : CMOS
CE, CA
Product Number (please contact us)
SG - 8002
series
Frequency
range
Supply
voltage
Function
:
1 MHz to 125 MHz
:
3.0 V / 3.3 V / 5.0 V
:
Output enable(OE) or Standby(
ST
)
CE
CA
Short
mass production lead time by PLL technology.
SG-Writer
available to purchase,
please contact Epson or local sales representative.
DC
JA
JC
Specifications (characteristics)
Item
Output frequency range
Supply voltage
Storage temperature
Operating temperature*1
Frequency tolerance
Current consumption
Output disable current
Stand-by current
Symbol
f
0
V
CC
T_stg
T_use
f_tol
I
CC
I_dis
I_std
Specifications
*2
PT
/
ST
PH
/
SH
PC
/
SC
1 MHz to 125 MHz
-
1 MHz to 125 MHz
-
-
1 MHz to 66.7 MHz
-
-
4.5 V to 5.5 V
2.7 V to 3.6 V
-55
C
to +125 °C
(SG-8002CA / JA / DC )
-55
C
to +100 °C
(SG-8002JC)
-40
C
to +125 °C
(SG-8002CE)
-20
C
to +70 °C / -40
C
to +85 °C
B:
50
10
-6
, C:
100
10
-6
M:
100
10
-6
M:
100
10
-6
40 mA Max.
(SG-8002CE)
28 mA Max.
45 mA Max.
(SG-8002CA / JC / JA / DC )
Conditions / Remarks
V
CC
= 4.5 V to 5.5 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 2.7 V to 3.6 V
Storage as single product.
-20
C
to +70
C
-40
C
to +85
C
(except SG-8002JC) *3
No load condition, Max. frequency
OE=GND (PT.PH,PC)
ST
=GND (ST,SH,SC)
TTL load: 1.4 V, Max. load condition
CMOS load:50 % V
CC
level, Max. load condition
30 mA Max.
50 µA Max.
40 % to 60 %
45 % to 55 %
-
-
-
16 mA Max.
Symmetry
*1
SYM
V
OH
V
OL
Output voltage
Output load condition
(TTL) *1
40 % to 60 %
45 % to 55 %
V
CC
-0.4 V Min.
0.4 V Max.
-
-
5 TTL Max.
L_TTL
5 TTL Max.
15 pF Max.
L_CMOS
15 pF Max.
V
IH
V
IL
tr/ tf
t_str
f_aging
25 pF Max
Output load condition
(CMOS) *1
Input voltage
Rise / Fall time
*1
Start-up time
Frequency aging
*1
15 pF Max.
70 % V
CC
Min.
20 % V
CC
Max.
-
I
OH
=-16 mA (PT,ST,PH,SH ) , -8 mA (PC,SC)
I
OL
=16 mA (PT,ST,PH,SH) , 8 mA (PC,SC)
Max. frequency and Max. Supply voltage
(SG-8002CE / CA / JA / DC )
f
0
90 MHz and Max. Supply voltage
(SG-8002JC )
Max. frequency and Max. Supply voltage
(SG-8002CE / JC)
Max. frequency and Max. Supply voltage
(SG-8002CA / JA / DC )
OE terminal or
ST
terminal
TTL load: 0.4 V to 2.4 V level
CMOS load: 20 % V
CC
to 80 % V
CC
level
Time at minimum supply voltage to be 0 s
+25
C,
V
CC
=5.0 V/ 3.3 V (PC,SC) First year
2.0 V Min.
0.8 V Max.
4 ns Max.
-
3 ns Max.
10 ms Max.
±5 × 10
-6
/ year Max.
Please refer to “Outline specifications” page for information regarding; operating temperature, available frequencies, symmetry, output load condi-
tions and rise/fall time.
*2
Please refer to “Jitter specifications and characteristics chart” page for PLL-PLL connection & Jitter specification.
*3
Please refer to “Outline specifications” for availability of tolerance “M”. A “Frequency checking” program on the Seiko Epson website
is also available.
Crystal oscillator
External dimensions and Recommended footprint
SG-8002CE
3.20.2
#4
#3
#3
(Unit:mm)
Ceramic SON 4pin 3.2x2.5x1.05 mm
C (ex.0.01 µF)
2.2
#4
#4
1.4
2.50.2
SC181A
#1
#2
0.7 0.9
E125.0C
#3
0.9
1.050.15
1.9
#2
#1
#1
2.4
#2
Resist
SG-8002CA
#4
#3
Ceramic SON 4pin 7.0x5.0x1.4 mm
#3
5.0
±0.2
1.4
#4
1.8
C
(ex. 0.01 μF)
2.6
E 125.000
PHC935C
#1
7.0
±0.2
#2
2.0
#2
5.08
#1
Resist
5.08
5.08
SG-8002JC
10.5 Max.
#4
#3
SOJ 4pin 10.5x5.8x2.7 mm
1.4
-0.15
+0.1
Package and pin compatible with SG-636.
1.3
E125.0000 C
2PH 9357B
#1
#2
The metal case inside of the molding com-
pound may be exposed on the top or bottom
of this product.
This purely cosmetic and does not have any
effect on quality, reliabil
i
ty or electrical specs.
4.6
5.0
5.8 Max.
2.7 Max.
0.51
5.08
0.05Min.
(1.0)
3.6
(1.0)
5.08
Note.
OE Pin (PT, PH, PC)
OE Pin = "H" or "open": Specified frequency output.
OE Pin = "L": Output is high impedance.
ST
Pin (ST, SH, SC)
ST
Pin = "H" or "open": Specified frequency output.
ST
Pin = "L": Output is low level (weak pull - down), oscillation
stops.
Pin map
Pin Connection
1
OE or
ST
2
GND
3
OUT
4
V
CC
To maintain stable operation, provide a
0.01uF to 0.1uF by-pass capacitor at a loca-
tion as near as possible to the power source
terminal of the crystal product (between V
CC
-
GND).
2.1
4.2
1.2
Crystal oscillator
SG-8002 Series
Model
Supply
volt-
age
Outline of specifications
Output load
condition
5TTL+15pF
15 pF
25 pF
25 pF
15 pF
(f0≤125 MHz)
(f0≤100 MHz)
(f0≤27 MHz)
40 % to 60 %
45 % to 55 %
45 % to 55 %
40 % to 60 %
45 % to 55 %
45 % to 55 %
40 % to 60 %
45 % to 55 %
Operating
temperature
-20 °C to +70 °C
Symmetry
(1.4 V, L_TTL=5 TTL+15 pF, f0≤125 MHz)
(1.4 V, L_TTL=5 TTL+15 pF, f0≤66.7 MHz)
(1.4 V, L_TTL=5 TTL+15 pF, f0≤27.0 MHz)
(50 % VCC, L_CMOS=15 pF, f0≤125 MHz)
(50 % VCC, L_CMOS=25 pF, f0≤66.7 MHz)
(50 % VCC, L_CMOS=25 pF, f0≤27.0 MHz)
(50 % VCC, L_CMOS=15 pF, f0≤125 MHz)
(50 % VCC, L_CMOS=15 pF, f0≤40 MHz)
2.0 ns Max.
4.0 ns Max.
3.0 ns Max.
Output rise time /
Output fall time
(0.8 V to 2.0 V,L_TTL=Max.)
(0.4 V to 2.4 V,L_TTL=Max.)
(20 % VCC to 80 % VCC,L_CMOS=Max.)
PT/ST
SG-8002CE
PH/SH
4.5 V to -40 °C to +85 °C
5.5 V
-20 °C to +70 °C
-40 °C to +85 °C
3.0 V to
3.6 V
PC/SC
-40 °C to +85 °C
2.7 V to
3.6 V
-20 °C to +70 °C
PT/ST
SG-8002CA
SG-8002JA
PH/SH
SG-8002DC
-40 °C to +85 °C
3.0 V to
3.6 V
PC/SC 2.7 V to -40 °C to +85 °C
3.6 V
PT/ST
4.5 V to
-20 °C to +70 °C
5.5 V
SG-8002JC
PH/SH
3.0 V to
3.6 V
-20 °C to +70 °C
PC/SC
2.7 V to
3.6 V
4.5 V to
5.5 V
-40 °C to +85 °C
-20 °C to +70 °C
3.0 ns Max.
(20 % VCC to 80 % VCC,L_CMOS=Max.)
40 % to 60 % (50 % VCC, L_CMOS=15 pF, f0≤66.7 MHz)
40 % to 60 %
5TTL+15pF (f0≤125 MHz)
↑
25 pF
(f0≤66.7 MHz)
45 % to 55 %
5 TTL+15 pF (f0≤40 MHz) 40 % to 60 %
15 pF
(f0≤55 MHz)
45 % to 55 %
40 % to 60 %
25 pF
(f0≤125 MHz)
↑
50 pF
(f0≤66.7 MHz)
45 % to 55 %
15 pF
(f0≤55 MHz)
40 % to 60 %
25 pF
(f0≤40 MHz)
45 % to 55 %
15 pF
40 % to 60 %
30 pF
(f0≤40 MHz)
45 % to 55 %
15 pF
(1.4 V, L_TTL=5 TTL+15 pF, f0≤125 MHz)
(1.4 V, L_CMOS=25 pF, f0≤66.7 MHz)
(1.4 V, L_TTL=5 TTL+15 pF, f0≤66.7 MHz)
(1.4 V, L_CMOS=15 pF, f0≤55.0 MHz)
(1.4 V, L_TTL=5 TTL+15 pF, f0≤40.0 MHz)
(50 % VCC, L_CMOS=25 pF, f0≤125 MHz)
(50 % VCC, L_CMOS=50 pF, f0≤66.7 MHz)
(50 % VCC, L_CMOS=25 pF, f0≤66.7 MHz)
(50 % VCC, L_CMOS=15 pF, f0≤55.0 MHz)
(50 % VCC, L_MOS=25 pF, f0≤40.0 MHz)
(50 % VCC, L_CMOS=15 pF, f0≤125 MHz)
(50 % VCC, L_CMOS=30 pF, f0≤40 MHz)
2.0 ns Max.
4.0 ns Max.
(0.8 V to 2.0 V,L_CMOS or L_TTL=Max.)
(0.4 V to 2.4 V,L_CMOS or L_TTL=Max.)
3.0 ns Max.
4.0 ns Max.
(20 % VCC to 80 % VCC,L_CMOS≤25pF)
(20 % VCC to 80 % VCC,L_CMOS=Max.)
40 % to 60 % (50 % VCC, L_CMOS=15 pF, f0≤66.7 MHz)
(1.4 V,L_CMOS=15 pF, f0≤125 MHz)
(1.4 V,L_TTL=5 TTL+15 pF, f0≤90.0 MHz)
(1.4 V,L_CMOS=25 pF, f0≤66.7 MHz)
(1.4 V,L_TTL=5 TTL+15 pF, f0≤66.7 MHz)
(50 % VCC, L_CMOS=15 pF, f0≤125 MHz)
(50 % VCC, L_CMOS=25 pF, f0≤90 MHz)
(50 % VCC, L_CMOS=50 pF, f0≤50 MHz)
(50 % VCC, L_CMOS=25 pF, f0≤66.7 MHz)
(50 % VCC, L_CMOS=15 pF, f0≤125 MHz)
(50 % VCC, L_CMOS=30 pF, f0≤40 MHz)
3.0 ns Max.
4.0 ns Max.
(20 % VCC to 80 % VCC,L_CMOS≤15pF)
(20 % VCC to 80 % VCC,L_CMOS=Max.)
40 % to 60 %
5TTL+15 pF (f0≤90 MHz)
↑
15 pF
(f0≤125 MHz)
↑
25 pF
(f0≤66.7 MHz)
45 % to 55 %
40 % to 60 %
15 pF
(f0≤125 MHz)
↑
25 pF
(f0≤90 MHz)
↑
50 pF
(f0≤66.7 MHz)
45 % to 55 %
15 pF
40 % to 60 %
30 pF
(f0≤40 MHz)
45 % to 55 %
15 pF
2.0 ns Max.
4.0 ns Max.
(0.8 V to 2.0 V,L_CMOS or L_TTL=Max.)
(0.4 V to 2.4 V,L_CMOS or L_TTL=Max.)
3.0 ns Max.
4.0 ns Max.
(20 % VCC to 80 % VCC,L_CMOS≤25pF)
(20 % VCC to 80 % VCC,L_CMOS=Max.)
40 % to 60 % (50 % VCC, L_CMOS=15 pF, f0≤66.7 MHz)
3.0 ns Max.
4.0 ns Max.
(20 % VCC to 80 % VCC,L_CMOS≤15pF)
(20 % VCC to 80 % VCC,L_CMOS=Max.)
Product Name
(Standard form)
⑤Supply
voltage
SG-8002 CE 125.000000MHz S C C
①
②
③
④⑤⑥
T,H 5.0 V Typ.
①Model
②Package
type
③Frequency
C
3.0 / 3.3 V Typ.
④Function
(P: Output enable, S:Standby)
⑤Supply
voltage
⑥Frequency
tolerance
/
Operating temperature
*As per table below.
⑥Frequency
tolerance
/
Operating temperature
B
C
M
±50 × 10
-6
/ -20 to +70°C
±100 × 10
-6
/ -20 to +70°C
±100 × 10
-6
/ -40 to +85°C
►
TABLE OF FREQUENCY RANGE*
Model(①,
②)
Function, Supply voltage(④,
⑤)
PT/ ST
PH/ SH
PC/SC
SG-8002CA
SG-8002JA
SG-8002DC
PT/ ST
PH/ SH
PC/ SC
PT/ ST
PH/ SH
PC/ SC
Supply voltage(⑤)
4.5 V to 5.5 V
3.0 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
3.0 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
3.0 V to 3.6 V
2.7 V to 3.6 V
Frequency(③)
1.0 MHz to 125 MHz
1.0 MHz to 27 MHz
1.0 MHz to 125 MHz
1.0 MHz to 66.7 MHz
1.0 MHz to 125 MHz
1.0 MHz to 55 MHz
1.0 MHz to 125 MHz
1.0 MHz to 66.7 MHz
1.0 MHz to 125 MHz
1.0 MHz to 125 MHz
1.0 MHz to 66.7 MHz
Frequency tolerance / Operating Temperature(⑥)
B,C
M
B,C,M
B,C
M
B,C,M
B,C
B,C
SG-8002CE
SG-8002JC
Crystal oscillator
SG-8002 series
Jitter specifications and characteristics chart
■
PLL-PLL connection
The SG-8002 series contains a PLL circuit and there are a few cases where the jitter value may be increased when this product
is connected to another PLL oscillator (cascading connection). We do not recommend this series for analog video clock use and
telecommunication synchronization. Please check in advance if the SG-8002 series jitter is acceptable to your application.
(Jitter specification of the SG-8002 series is max.250 ps/CL=15 pF)
Jitter Specifications
Model
PT
/
PH
ST
/
SH
SC
/
PC
Supply
Voltage
5.0 V
0.5
V
Jitter Item
Cycle to cycle
Peak to peak
Specifications
150 ps Max.
200 ps Max.
200 ps Max.
250 ps Max.
200 ps Max.
250 ps Max.
Remarks
33 MHz
f
0
125 MHz, L_CMOS=15 pF
1.0 MHz
f
0
< 33 MHz, L_CMOS=15 pF
33 MHz
f
0
125 MHz, L_CMOS=15 pF
1.0 MHz
f
0
< 33 MHz, L_CMOS=15 pF
1.0 MHz
f
0
125 MHz, L_CMOS=15 pF
1.0 MHz
f
0
125 MHz, L_CMOS=15 pF
3.3 V
0.3
V
Cycle to cycle
Peak to peak
■
Remarks on noise management for power supply line
It is not recommended to insert filters or other devices in the power supply line as a counter measure for EMI noise reduction.
This may cause high-frequency impedance of the power supply line and negatively affect stable oscillation.
When using this measure please evaluate the circuitry and device behavior in the circuit to verify and effects on oscillation.
Start up time (0 % V
CC
to 90 % V
CC
) of power source should be more than 150
s.
■
SG-8002 series Characteristics chart
50
40
Current consumption
(V
CC
=5.0V)
60
Symmetry 5.0 V CMOS Level
25 pF
3.0
Output Rise time (CMOS Level)
Symmetry (%)
55
50
45
40
0
20
50 pF
2.5
I
CC
(mA)
Rise time (ns)
30
20
10
0
50
40
20
40 60 80 100 120 140
Frequency(MHz)
15 pF
3.0 V
3.3 V
3.6 V
2.7 V
4.5 V
5.0 V
5.5 V
2.0
1.5
40 60 80 100 120 140
Frequency(MHz)
1.0
10 15 20 25 30 35 40 45
50 55
Disable Current
(V
CC
=5.0V)
60
Symmetry 3.3 V CMOS Level
3.0
Load capacitance (pF)
Output Fall time (CMOS Level)
3.0 V
3.3 V
3.6 V
4.5 V
5.0 V
5.5 V
Symmetry (%)
55
30 pF
I
_dis
(mA)
30
20
10
0
50
40
20
40 60 80 100 120 140
Frequency(MHz)
Stand-by Current
50
15 pF
Fall Time (ns)
2.5
45
40
0
20
40 60 80 100 120 140
Frequency(MHz)
2.0
2.7 V
1.5
60
Symmetry 5.0V TTL Level
1.0
10 15 20 25 30 35 40 45
50 55
Load capacitance (pF)
Symmetry (%)
55
50
45
40
0
20
I
_std
(A)
25 pF
15 pF
2.0
Output Rise time (TTL Level)
4.5 V
5.0 V
5.5 V
30
20
10
2.5
3.0 3.5 4.0 4.5 5.0
V
CC
(V)
5.5 6.0
Rise Time (ns)
1.5
1.0
40 60 80 100 120 140
Frequency(MHz)
10
2.0
Additional Value (mA)
Output load vs. Additional Current consumption
20
V
CC
=5.0 V
18
25 pF
16
14
50 pF
12
15 pF
10
30 pF
8
6
4
2
Voltage coefficient [
V
CC
vs I_dis,I_std ]
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.5
I_dis(Va)=Times(Va)×I_dis(5.0V)
I_std(Va)=Times(Va)×I_std(5.0V)
15
20
25
Load capacitance (pF)
Output Fall time (TTL Level)
30
Fall Time (ns)
Times
1.5
4.5 V
5.0 V
5.5 V
1.0
0
20
40 60 80 100 120 140
Frequency(MHz)
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V
CC
(V)
10
15
20
25
Load capacitance (pF)
30
FPGA/CPLD
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