A3950
DMOS Full-Bridge Motor Driver
Features and Benefits
▪
▪
▪
▪
▪
▪
▪
▪
▪
Low R
DS(on)
outputs
Overcurrent protection
Motor lead short-to-supply protection
Short-to-ground protection
Sleep function
Synchronous rectification
Diagnostic output
Internal undervoltage lockout (UVLO)
Crossover-current protection
Description
Designed for PWM (pulse width modulated) control of DC
motors, the A3950 is capable of peak output currents to ±2.8 A
and operating voltages to 36 V.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a DC motor with externally
applied PWM control signals. Internal synchronous rectification
control circuitry is provided to lower power dissipation during
PWM operation.
Internal circuit protection includes motor lead short-to-
supply / short-to-ground, thermal shutdown with hysteresis,
undervoltage monitoring of V
BB
and V
CP
, and crossover-current
protection.
The A3950 is supplied in a thin profile (<1.2 mm overall height)
16 pin TSSOP package (LP), and a very thin (0.75 mm nominal
height) QFN package. Both packages provide an exposed pad
for enhanced thermal dissipation, and are lead (Pb) free with
100% matte tin leadframe plating.
Packages:
Package LP, 16 pin TSSOP
with Exposed Thermal Pad
Package EU, 16 pin QFN
with Exposed Thermal Pad
Approximate Scale 1:1
Typical Application Diagrams
V
BB
0.1 µF
50 V
NFAULT
GND
CP2
CP1
OUTB
SENSE
OUTA
VBB
NC
0.1 µF
50 V
100 µF
50 V
NC
VREG
VCP
0.1 µF
50 V
0.22 µF
25 V
0.22 µF
25 V
V
BB
NFAULT
V
DD
5 kΩ
PHASE
GND
SLEEP
ENABLE
MODE
VREG
VCP
V
DD
5 kΩ
MODE
PHASE
GND
SLEEP
ENABLE
OUTA
SENSE
A3950
EU Package
A3950
LP Package
GND
CP2
CP1
OUTB
VBB
0.1 µF
50 V
0.1 µF
50 V
100 µF
50 V
0.1 µF
50 V
Package EU
Package LP
A3950DS, Rev. 7
A3950
DMOS Full-Bridge Motor Driver
Selection Guide
Part Number
A3950SLPTR-T
A3950SEUTR-T
Packing
13 in. reel, 4000 pieces / reel
7 in. reel, 1500 pieces / reel
Package
16 pin TSSOP with exposed thermal pad
16 pin QFN with exposed thermal pad
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Output Current
Transient Output Current
Sense Voltage
VBB to OUTx
OUTx to SENSE
Logic Input Voltage
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
V
IN
T
A
T
J
(max)
T
stg
Range S
Symbol
V
BB
I
OUT
I
OUT
V
SENSE
T
W
< 500 ns
Notes
Rating
36
2.8
6
±500
36
36
–0.3 to 7
–20 to 85
150
–40 to 125
Units
V
A
A
mV
V
V
V
ºC
ºC
ºC
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
A3950
DMOS Full-Bridge Motor Driver
Functional Block Diagram
0.1 µF
CP1
CP2
Charge
Pump
VCP
0.1 µF
VREG
0.22 µF
25 V
MODE
Low-Side
Gate Supply
Bias
Supply
VBB
Load Supply
0.1 µF
100 µF
PHASE
Control Logic
V
DD
ENABLE
5 kΩ
SLEEP
5 kΩ
NFAULT
UVLO
STB
STG
TSD Warning
VBB
OUTA
OUTB
SENSE
OUTA
OUTB
SENSE
Motor Lead
Protection
GND
Pad
GND
Terminal List Table
Name
NFAULT
MODE
PHASE
GND
SLEEP
ENABLE
OUTA
SENSE
VBB
OUTB
CP1
CP2
VCP
VREG
NC
Pad
Number
EU
15
16
1
2, 12
3
4
6
7
8
9
10
11
13
14
5
–
LP
1
2
3
4,13
5
6
7
8
9
10
11
12
14
15
16
–
Description
Fault output, open drain
Logic input
Logic input for direction control
Ground
Logic input
Logic input
DMOS full-bridge output A
Power return
Load supply voltage
DMOS full-bridge output B
Charge pump capacitor terminal
Charge pump capacitor terminal
Reservoir capacitor terminal
Regulator decoupling terminal
No connection
Exposed pad for thermal dissipation connect to GND pins
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A3950
DMOS Full-Bridge Motor Driver
1
For
ELECTRICAL CHARACTERISTICS at TJ = 25°C, V
BB
= 8 to 36 V,
unless noted otherwise
Characteristics
Symbol
Test Conditions
f
PWM
< 50 kHz
Motor Supply Current
I
BB
Charge pump on, outputs disabled
Sleep mode
V
IH
PHASE, ENABLE, MODE Input
Voltage
V
IL
V
IH
SLEEP Input Voltage
V
IL
I
IH
V
IN
= 2.0 V
PHASE, MODE Input Current
1
I
IL
V
IN
= 0.8 V
I
IH
V
IN
= 2.0 V
ENABLE Input Current
I
IL
V
IN
= 0.8 V
I
IH
V
IN
= 2.7 V
SLEEP Input Current
I
IL
V
IN
= 0.8 V
NFAULT Output Voltage
V
OL
I
sink
= 1.0 mA
Input Hysteresis, except SLEEP
V
IHys
Source driver, I
OUT
= -2.8 A, T
J
=25°C
Source driver, I
OUT
= -2.8 A, T
J
=125°C
Output On Resistance
R
DS(on)
Sink driver, I
OUT
= 2.8 A, T
J
=25°C
Sink driver, I
OUT
= 2.8 A, T
J
=125°C
Source diode, I
f
= –2.8 A
Body Diode Forward Voltage
1
V
f
Sink diode, I
f
= 2.8 A
PWM, change to source or sink ON
Propagation Delay Time
t
pd
PWM, change to source or sink OFF
Crossover Delay
t
COD
Protection Circuitry
UVLO Threshold
V
UV
V
BB
increasing
UVLO Hysteresis
V
UVHys
2
Overcurrent Threshold
I
OCP
Overcurrent Protection Period
t
OCP
Thermal Warning Temperature
T
JW
Temperature increasing
Thermal Warning Hysteresis
T
JWHys
Recovery = T
JW
– T
JWHys
Thermal Shutdown Temperature
T
JTSD
Temperature increasing
Thermal Shutdown Hysteresis
T
JTSDHys
Recovery = T
JTSD
– T
JTSDHys
Min. Typ. Max. Units
–
6
8.5
mA
–
3
4.5
mA
–
–
10
µA
2.0
–
–
V
–
–
0.8
V
2.7
–
–
V
–
–
0.8
V
–
<1.0
20
µA
–20 <–2.0 20
µA
–
40
100
µA
–
16
40
µA
–
27
50
µA
–
<1
10
µA
–
–
0.4
V
100 150 250
mV
–
0.35 0.48
Ω
–
0.55 0.8
Ω
–
0.3 0.43
Ω
–
0.45 0.7
Ω
–
–
1.4
V
–
–
1.4
V
–
600
–
ns
–
100
–
ns
–
500
–
ns
–
–
3
–
–
–
–
–
6.5
250
–
1.2
160
15
175
15
–
–
–
–
–
–
–
–
V
mV
A
ms
°C
°C
°C
°C
2
Overcurrent
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
protection is tested at 25°C in a restricted range and guaranteed by characterization.
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic
Symbol
Test Conditions*
Preliminary: EU package, 4-layer PCB based on JEDEC standard
Package Thermal Resistance
R
θJA
LP package, 4-layer PCB based on JEDEC standard
LP package, 2-layer PCB with 3.8 in.
2
copper both sides, connected by
thermal vias
*Additional thermal data available on the Allegro Web site.
Value
30
34
43
Units
ºC/W
ºC/W
ºC/W
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
A3950
DMOS Full-Bridge Motor Driver
Timing Diagram: PWM Control
SLEEP
ENABLE
PHASE
MODE
V
BB
V
OUTA
0
V
BB
V
OUTB
0
I
OUTX
0
A
1
2
3
4
5
6
7
8
9
V
BB
1 5
6
OutA
3
2 4
OutB
OutA
8
V
BB
7
OutB
9
A Charge pump and VREG power-on delay (≈200 µs)
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
