Product Brief
ProASIC
®
3 Flash Family FPGAs
with Optional Soft ARM
®
Support
Features and Benefits
High Capacity
•
•
•
•
•
•
•
•
•
•
•
30 k to 1 Million System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
Live at Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
1 kbit of FlashROM with Synchronous Interfacing
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI (except A3P030)
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except A3P030 and ARM
®
-
enabled ProASIC
®
3 devices) via JTAG (IEEE 1532–
compliant)
FlashLock
®
to Secure FPGA Contents
Core Voltage for Low Power
Support for 1.5-V-Only Systems
Low-Impedance Flash Switches
Segmented, Hierarchical Routing and Clock Structure
Ultra-Fast Local and Long-Line Network
Enhanced High-Speed, Very-Long-Line Network
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
®
Advanced I/O
700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—Up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X (except
A3P030), and LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, BLVDS, and
M-LVDS (A3P250 and above)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os (A3P030 only)
Programmable Output Slew Rate (except A3P030) and
Drive Strength
Weak Pull-Up/Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages Across the ProASIC3 Family
Six CCC Blocks, One with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay
Capabilities and External Feedback, Multiply/Divide,
Delay Capabilities, and External Feedback
Wide Input Frequency Range (1.5 MHz to 350 MHz)
CoreMP7Sd (with debug) and CoreMP7S (without debug
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2,
×4, ×9, and ×18 Organizations Available)
True Dual-Port SRAM (except ×18)
24 SRAM and FIFO Configurations with Synchronous
Operation up to 350 MHz
CoreMP7Sd (with debug) and CoreMP7S (without
debug)
Reprogrammable Flash Technology
On-Chip User Nonvolatile Memory
High Performance
In-System Programming (ISP) and Security
Clock Conditioning Circuit (CCC) and PLL (except A3P030)
•
•
•
•
•
•
•
Low Power
SRAMs and FIFOs (except A3P030)
High-Performance Routing Hierarchy
Soft ARM7™ Core Support in M7 ProASIC3 Devices
•
Table 1 •
ProASIC3 Product Family
A3P030
A3P060
A3P125
A3P250
M7A3P250
30 k
768
–
–
1k
–
–
6
2
81
QN132
VQ100
60 k
1,536
18
4
1k
Yes
1
18
2
96
QN132
VQ100
TQ144
FG144
125 k
3,072
36
8
1k
Yes
1
18
2
133
QN132
VQ100
TQ144
PQ208
FG144
250 k
6,144
36
8
1k
Yes
1
18
4
157
QN132
5
VQ100
PQ208
FG144,
FG256
5
PQ208
FG144, FG256,
FG484
PQ208
FG144, FG256,
FG484
PQ208
FG144, FG256,
FG484
ProASIC3 Devices
ARM
®
-Enabled
ProASIC3 Devices
1
System Gates
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
2
Integrated PLL in CCCs
VersaNet Globals
3
I/O Banks
Maximum User I/Os
Package Pins
QFN
VQFP
TQFP
PQFP
FBGA
A3P400
M7A3P400
400 k
9,216
54
12
1k
Yes
1
18
4
194
A3P600
M7A3P600
600 k
13,824
108
24
1k
Yes
1
18
4
235
A3P1000
M7A3P1000
1M
24,576
144
32
1k
Yes
1
18
4
300
Notes:
1. Refer to the
CoreMP7
datasheet for more information.
2. AES is not available for ARM-enabled ProASIC3 devices.
3. Six chip (main) and three quadrant global networks are available for A3P060 and above.
4. For higher densities and support of additional features, refer to the
ProASIC3E Flash FPGAs
datasheet.
5. The M7A3P250 device does not support this package.
May 2007
© 2007 Actel Corporation
1
See the Actel website for the latest version of the datasheet.
ProASIC3 Flash Family FPGAs
I/Os Per Package
1
ProASIC3
Devices
ARM-Enabled
ProASIC3
Devices
A3P030
A3P060
A3P125
A3P250
3
A3P400
3
A3P600
A3P1000
M7A3P250
3, 4
Differential I/O Pairs
M7A3P400
3
Differential I/O Pairs
M7A3P600
Differential I/O Pairs
M7A3P1000
Differential I/O Pairs
–
–
–
35
25
44
74
I/O Type
Single-Ended I/O
2
Single-Ended I/O
2
Single-Ended I/O
2
Single-Ended I/O
2
–
–
–
154
97
177
300
Single-Ended I/O
Single-Ended I/O
Package
QN132
VQ100
TQ144
PQ208
FG144
FG256
FG484
Notes:
1.
2.
3.
4.
5.
81
77
–
–
–
–
–
80
71
91
–
96
–
–
84
71
100
133
97
–
–
Single-Ended I/O
87
68
–
151
97
157
–
19
13
–
34
24
38
–
–
–
–
151
97
178
194
–
–
–
34
25
38
38
–
154
97
177
235
–
–
–
35
25
43
60
Each used differential I/O pair reduces the number of single-ended I/Os available by two.
For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15.
The M7A3P250 device does not support FG256 or QN132 packages.
FG256 and FG484 are footprint-compatible packages.
"G" indicates RoHS-compliant packages. Refer to
"ProASIC3 Ordering Information" on page 3
for the location of the "G" in the part
number.
2
P ro du ct B ri e f
ProASIC3 Flash Family FPGAs
ProASIC3 Ordering Information
A3P1000
_
1
FG
G
144
I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C)
I = Industrial (
–
40°C to +85°C)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant (Green) Packaging
Package Type
QN = Quad Flat Pack No Leads (0.5 mm pitch)
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
TQ = Thin Quad Flat Pack (0.5 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
F = 20% Slower than Standard*
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
ProASIC3 Devices
A3P030 = 30,000 System Gates
A3P060 = 60,000 System Gates
A3P125 = 125,000 System Gates
A3P250 = 250,000 System Gates
A3P400 = 400,000 System Gates
A3P600 = 600,000 System Gates
A3P1000 = 1,000,000 System Gates
ARM-Enabled ProASIC3 Devices
M7A3P250 =
M7A3P400 =
M7A3P600 =
M7A3P1000 =
250,000 System Gates
400,000 System Gates
600,000 System Gates
1,000,000 System Gates
Note:
*The DC and switching characteristics for the –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions
might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial
temperature range.
P ro du c t B ri ef
3
ProASIC3 Flash Family FPGAs
Temperature Grade Offerings
A3P030
Package
QN132
VQ100
TQ144
PQ208
FG144
FG256
FG484
Notes:
1. The M7A3P250 device does not support FG256 or QN132 packages.
2. C = Commercial temperature range: 0°C to 70°C
3. I = Industrial temperature range: –40°C to 85°C
C, I
C, I
–
–
–
–
–
C, I
C, I
C, I
–
C, I
–
–
C, I
C, I
C, I
C, I
C, I
–
–
A3P060
A3P125
A3P250
M7A3P250
1
C, I
C, I
–
C, I
C, I
C, I
–
A3P400
M7A3P400
–
–
–
C, I
C, I
C, I
C, I
A3P600
M7A3P600
–
–
–
C, I
C, I
C, I
C, I
A3P1000
M7A3P1000
–
–
–
C, I
C, I
C, I
C, I
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
2
I
3
Notes:
1. The DC and switching characteristics for the –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions
might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial
temperature range.
2. C = Commercial temperature range: 0°C to 70°C
3. I = Industrial temperature range: –40°C to 85°C
–F
1
✓
–
Std.
✓
✓
–1
✓
✓
–2
✓
✓
Datasheet references made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part
numbers start with M7.
Contact your local Actel representative for device availability (http://www.actel.com/contact/default.aspx).
4
P ro du ct B ri e f
ProASIC3 Flash Family FPGAs
Introduction and Overview
General Description
ProASIC3, the third-generation family of Actel Flash
FPGAs, offers performance, density, and features beyond
those of the ProASIC
PLUS®
family. Nonvolatile Flash
technology gives ProASIC3 devices the advantage of
being a secure, low-power, single-chip solution that is
live at power-up (LAPU). ProASIC3 is reprogrammable
and offers time-to-market benefits at an ASIC-level unit
cost. These features enable designers to create high-
density systems using existing ASIC or FPGA design flows
and tools.
ProASIC3
devices
offer
1
kbit
of
on-chip,
reprogrammable, nonvolatile FlashROM storage as well
as clock conditioning circuitry based on an integrated
phase-locked loop (PLL). The A3P030 device has no PLL or
RAM support. ProASIC3 devices have up to 1 million
system gates, supported with up to 144 kbits of true
dual-port SRAM and up to 288 user I/Os.
ProASIC3 devices support the ARM7 soft IP core in
devices with at least 250 k system gates. The ARM-
enabled devices have Actel ordering numbers that begin
with M7A3P and do not support AES decryption.
bitstream that can be easily copied. ProASIC3 devices
incorporate FlashLock, which provides a unique
combination of reprogrammability and design security
without external overhead, advantages that only an
FPGA with nonvolatile Flash programming can offer.
ProASIC3 devices utilize a 128-bit Flash-based lock and a
separate AES key to secure programmed intellectual
property and configuration data. In addition, all
FlashROM data in ProASIC3 devices can be encrypted
prior to loading, using the industry-leading AES-128
(FIPS192) bit block cipher encryption standard. The AES
standard was adopted by the National Institute of
Standards and Technology (NIST) in 2000 and replaces
the 1977 DES standard. ProASIC3 devices have a built-in
AES decryption engine and a Flash-based AES key that
make them the most comprehensive programmable logic
device security solution available today. ProASIC3 devices
with AES-based security allow for secure, remote field
updates over public networks such as the Internet, and
ensure that valuable IP remains out of the hands of
system overbuilders, system cloners, and IP thieves. The
contents of a programmed ProASIC3 device cannot be
read back, although secure design verification is possible.
ARM-enabled ProASIC3 devices do not support user-
controlled AES security mechanisms. Since the ARM core
must be protected at all times, AES encryption is always
on for the core logic, so bitstreams are always encrypted.
There is no user access to encryption for the FlashROM
programming data.
Security, built into the FPGA fabric, is an inherent
component of the ProASIC3 family. The Flash cells are
located beneath seven metal layers, and many device
design and layout techniques have been used to make
invasive attacks extremely difficult. The ProASIC3 family,
with FlashLock and AES security, is unique in being highly
resistant to both invasive and noninvasive attacks. Your
valuable IP is protected and secure, making remote ISP
possible. An ProASIC3 device provides the most
impenetrable security for programmable logic designs.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost,
performance, and ease of use. Unlike SRAM-based
FPGAs, Flash-based ProASIC3 devices allow all
functionality to be live at power-up; no external boot
PROM is required. On-board security mechanisms
prevent access to all the programming information and
enable secure remote updates of the FPGA logic.
Designers can perform secure remote in-system
reprogramming to support future design iterations and
field upgrades with confidence that valuable intellectual
property (IP) cannot be compromised or copied. Secure
ISP can be performed using the industry-standard AES
algorithm. The ProASIC3 family device architecture
mitigates the need for ASIC migration at higher user
volumes. This makes the ProASIC3 family a cost-effective
ASIC replacement solution, especially for applications in
the consumer, networking/ communications, computing,
and avionics markets.
Single Chip
Flash-based FPGAs store their configuration information
in on-chip Flash cells. Once programmed, the
configuration data is an inherent part of the FPGA
structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based
FPGAs). Therefore, Flash-based ProASIC3 FPGAs do not
require system configuration components such as
EEPROMs
or
microcontrollers
to
load
device
configuration data. This reduces bill-of-materials costs
Security
The nonvolatile, Flash-based ProASIC3 devices do not
require a boot PROM, so there is no vulnerable external
P r o du c t B r i ef
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
