Am29SL400C
Data Sheet
The following document contains information on Spansion memory products. Although the document
is marked with the name of the company that originally developed the specification, Spansion will
continue to offer these products to existing customers.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
Am29SL400C_00
Revision
A
Amendment
6
Issue Date
January 23, 2007
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29SL400C
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8
Volt-only Super Low Voltage Flash Memory
Distinctive Characteristics
■
Single power supply operation
— 1.65 to 2.2 V for read, program, and erase operations
— Ideal for battery-powered applications
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes
and verifies data at specified addresses
■
Manufactured on 0.32 µm process technology
■
High performance
— Access times as fast as 100 ns
■
Ultra low power consumption (typical values at
5 MHz)
—
—
—
—
1 µA Automatic Sleep Mode current
1 µA standby mode current
5 mA read current
20 mA program/erase current
■
Minimum 1,000,000 erase cycle guarantee per
sector
■
20-year data retention at 125°C
■
Package option
— 48-ball FBGA
— 48-pin TSOP
■
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven
64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and seven
32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent any
program or erase operations within that sector
Sectors can be locked in-system or via programming
equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash
— Superior inadvertent write protection
■
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
■
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
■
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
■
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array
data
■
Top or bottom boot block configurations
available
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may
be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
Am29SL400C_00
Rev:
A
Amendment:
6
Issue Date:
January 23, 2007
D A T A
S H E E T
General Description
The Am29SL400C is an 4Mbit, 1.8 V volt-only Flash memory
organized as 524,288 bytes or 262,144 words. The device is
offered in 48-pin TSOP and 48-ball FBGA packages. The
word-wide data (x16) appears on DQ15–DQ0; the byte-wide
(x8) data appears on DQ7–DQ0. This device is designed to
be programmed and erased in-system with a single 1.8 volt
V
CC
supply. No V
PP
is required for write or erase operations.
The device can also be programmed in standard EPROM
programmers.
The standard device offers access times of 100, 110, 120,
and 150 ns, allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the device
has separate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls.
The device requires only a
single 1.8 volt power supply
for
both read and write functions. Internally generated and regu-
lated voltages are provided for the program and erase opera-
tions.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Commands
are written to the command register using standard micro-
processor write timings. Register contents serve as input to
an internal state-machine that controls the erase and pro-
gramming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
Device programming occurs by executing the program com-
mand sequence. This initiates the
Embedded Program
al-
gorithm—an internal algorithm that automatically times the
program pulse widths and verifies proper cell margin. The
Unlock Bypass
mode facilitates faster programming times
by requiring only two write cycles to program data instead of
four.
Device erasure occurs by executing the erase command se-
quence. This initiates the
Embedded Erase
algorithm—an
internal algorithm that automatically preprograms the array
(if it is not already programmed) before executing the erase
operation. During erase, the device automatically times the
erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase op-
eration is complete by observing the RY/BY# pin, or by read-
ing the DQ7 (Data# Polling) and DQ6 (toggle)
status bits.
After a program or erase cycle has been completed, the de-
vice is ready to read array data or accept another command.
The
sector erase architecture
allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection
measures include a low V
CC
de-
tector that automatically inhibits write operations during
power transitions. The
hardware sector protection
feature
disables both program and erase operations in any combina-
tion of the sectors of memory. This can be achieved in-sys-
tem or via programming equipment.
The
Erase Suspend
feature enables the user to put erase
on hold for any period of time to read data from, or program
data to, any sector that is not selected for erasure. True
background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation in
progress and resets the internal state machine to reading
array data. The RESET# pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read the boot-up
firmware from the Flash memory.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the
automatic sleep mode.
The system can
also place the device into the
standby mode.
Power con-
sumption is greatly reduced in both these modes.
AMD’s Flash technology combines years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using
hot electron injection.
2
Am29SL400C
Am29SL400C_00_A6 January 23, 2007
D A T A
S H E E T
TABLE OF CONTENTS
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA Packages 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29SL400C Device Bus Operations ............9
Reading Toggle Bits DQ6/DQ2 ............................ 20
Figure 6. Toggle Bit Algorithm..................................... 21
DQ5: Exceeded Timing Limits .............................. 21
DQ3: Sector Erase Timer ..................................... 21
Table 6. Write Operation Status ..................................22
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 23
Figure 7. Maximum Negative Overshoot Waveform ... 23
Figure 8. Maximum Positive Overshoot Waveform ..... 23
Word/Byte Configuration ........................................ 9
Requirements for Reading Array Data ................... 9
Writing Commands/Command Sequences ............ 9
Program and Erase Operation Status .................. 10
Standby Mode ...................................................... 10
Automatic Sleep Mode ......................................... 10
RESET#: Hardware Reset Pin ............................. 10
Output Disable Mode ............................................ 10
Table 2. Am29SL400CT Top Boot Block
Sector Address Table ..................................................11
Table 3. Am29SL400CB Bottom Boot Block
Sector Address Table ..................................................11
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. I
CC1
Current vs. Time (Showing Active and Au-
tomatic Sleep Currents)............................................... 25
Figure 10. Typical I
CC1
vs. Frequency ........................ 25
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. Test Setup.................................................. 26
Table 7. Test Specifications ........................................26
Key to Switching Waveforms ................................ 26
Figure 12. Input Waveforms
and Measurement Levels ............................................ 26
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13. Read Operations Timings .......................... 27
Figure 14. RESET# Timings........................................ 28
Figure 15. BYTE# Timings for Read Operations......... 29
Figure 16. BYTE# Timings for Write Operations ......... 29
Figure 17. Program Operation Timings ....................... 31
Figure 18. Chip/Sector Erase Operation Timings........ 32
Figure 19. Data# Polling Timings
(During Embedded Algorithms) ................................... 33
Figure 20. Toggle Bit Timings
(During Embedded Algorithms) ................................... 33
Figure 21. DQ2 vs. DQ6.............................................. 34
Autoselect Mode ................................................... 11
Table 4. Am29SL400C Autoselect Codes
(High Voltage Method) ................................................12
Sector Protection/Unprotection ............................ 12
Temporary Sector Unprotect ................................ 12
Figure 2. Temporary Sector Unprotect Operation....... 14
Hardware Data Protection .................................... 14
Command Definitions . . . . . . . . . . . . . . . . . . . . . 15
Reading Array Data .............................................. 15
Reset Command .................................................. 15
Autoselect Command Sequence .......................... 15
Word/Byte Program Command Sequence ........... 15
Figure 3. Program Operation ...................................... 16
Temporary Sector Unprotect ................................ 34
Figure 22. Temporary Sector Unprotect
Timing Diagram ........................................................... 34
Figure 23. Sector Protect/Unprotect Timing Diagram . 35
Figure 24. Alternate CE# Controlled
Write Operation Timings.............................................. 37
Chip Erase Command Sequence ......................... 16
Sector Erase Command Sequence ...................... 16
Figure 4. Erase Operation........................................... 17
Command Definitions ........................................... 18
Table 5. Am29SL400C Command Definitions ............18
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 19
DQ7: Data# Polling ............................................... 19
Figure 5. Data# Polling Algorithm ............................... 19
RY/BY#: Ready/Busy# ......................................... 19
DQ6: Toggle Bit I .................................................. 20
DQ2: Toggle Bit II ................................................. 20
Erase and Programming Performance . . . . . . . . 38
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 39
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40
TS048—48-Pin Standard TSOP .......................... 40
FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
6 x 8 mm Package ................................................ 41
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 42
January 23, 2007 Am29SL400C_00_A6
Am29SL400C
3
NXP MCU
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