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SY100E417JITR

产品描述PECL to LVPECL Transceiver, 5 Func, Complementary Output, ECL, PQCC28
产品类别模拟混合信号IC    驱动程序和接口   
文件大小72KB,共5页
制造商Micrel ( Microchip )
官网地址https://www.microchip.com
相似器件已查找到7个与SY100E417JITR功能相似器件
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SY100E417JITR概述

PECL to LVPECL Transceiver, 5 Func, Complementary Output, ECL, PQCC28

SY100E417JITR规格参数

参数名称属性值
是否Rohs认证不符合
包装说明QCCJ, LDCC28,.5SQ
Reach Compliance Code_compli
ECCN代码EAR99
最大延迟0.68 ns
接口集成电路类型PECL TO LVPECL TRANSCEIVER
JESD-30 代码S-PQCC-J28
JESD-609代码e0
长度11.48 mm
湿度敏感等级1
位数1
功能数量5
端子数量28
最高工作温度85 °C
最低工作温度-40 °C
输出锁存器或寄存器NONE
输出极性COMPLEMENTARY
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装等效代码LDCC28,.5SQ
封装形状SQUARE
封装形式CHIP CARRIER
峰值回流温度(摄氏度)240
电源3.3/5,5 V
认证状态Not Qualified
座面最大高度4.57 mm
最大供电电压5.5 V
最小供电电压4.5 V
标称供电电压5 V
表面贴装YES
技术ECL
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn85Pb15)
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
处于峰值回流温度下的最长时间30
宽度11.48 mm
Base Number Matches1

文档解析

SY100E417是一款高性能五通道PECL到LVPECL电平转换器,专为需要将5V PECL信号转换为3.3V LVPECL信号的应用设计。该设备采用全差分架构,确保信号完整性和低噪声性能,适用于高速数据通信系统。它支持差分输入和输出,并提供VBB参考电压输出,以方便单端输入配置,增强系统灵活性。 在技术特性方面,SY100E417具有500ps的典型传播延迟,最小输入峰值电压为150mV,工作温度范围覆盖-40°C至85°C。电源配置要求VCC和VCC_VBB连接到5V电源,VCCO连接到3.3V电源,所有电源引脚需 bypass 0.01μF电容以确保稳定运行。设备还具备高共模输入范围,支持1.2V至VCC-0.2V,适应各种信号环境。 典型应用包括网络设备、数据中心互连和测试仪器,其中需要将传统PECL接口转换为低电压LVPECL标准,以降低功耗和提高集成度。其可靠性和高速性能使其成为现代通信系统的理想选择。

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QUINT LVPECL-TO-PECL
OR PECL-TO-LVPECL
TRANSLATOR
FEATURES
s
s
s
s
s
3.3V and 5V power supplies required
Also, supports LVPECL-to-PECL translation
500ps propagation delays
Fully differential design
Differential line receiver capability
SY100E417
FINAL
DESCRIPTION
The SY100E417 is a quint LVPECL-to-PECL translator.
It can also be used as a quint PECL-to-LVPECL translator.
The device receives standard PECL signals and translates
them to differential LVPECL output signals (or vice versa).
The SY100E417 can also be used as a differential line
receiver for PECL-to-PECL or LVPECL-to-LVPECL signals.
However, please note that for the latter we will need two
different power supplies. Please refer to Function Table for
more details.
A V
BB
output is provided for interfacing single ended
input signals. If a single ended input is to be used, the V
BB
output should be connected to the Dn input and the active
signal will drive the Dn input. When used, the V
BB
should
be bypassed to V
CC
via a 0.01µF capacitor. The V
BB
is
designed to act as a switching reference for the SY100E417
under single ended input conditions. As a result, the pin
can only source/sink 0.5mA of current.
To accomplish the PECL-to-LVPECL level translation,
the SY100E417 requires three power rails. The V
CC
and
V
CC
_V
BB
supply is to be connected to the standard PECL
supply, the 3.3V supply is to be connected to the V
CCO
supply, and GND is connected to the system ground plane.
Both the V
CC
and V
CCO
should be bypassed to ground with
a 0.01µF capacitor.
To accomplish the LVPECL-to-PECL level translation,
the SY100E417 requires three power rails as well. The 5.0V
supply is connected to the V
CC
and V
CCO
pins, 3.3V supply
is connected to the V
CC
_V
BB
pin and GND is connected to
the system ground plane. V
CC
_V
BB
is used to provide a
proper V
BB
output level if a single ended input is used.
V
CC
_V
BB
= 3.3V is only required for single-ended LVPECL
input. For differential LVPECL input, V
CC
_V
BB
can be either
3.3V or 5.0V.
Under open input conditions, the Dn input will be biased
at a V
CC
/2 voltage level and the Dn input will be pulled to
GND. This condition will force the "Qn" output low, ensuring
stability.
s
Available in 28-pin PLCC package
BLOCK DIAGRAM
D
0
D
0
D
1
D
1
D
2
D
2
D
3
D
3
D
4
D
4
V
BB
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
FUNCTION TABLE
Function
PECL-to-LVPECL
LVPECL-to-PECL
PECL-to-PECL
LVPECL-to-LVPECL
Vcc
5.0V
5.0V
5.0V
5.0V
Vcco
3.3V
5.0V
5.0V
3.3V
Vcc_V
BB
5.0V
3.3V
5.0V
3.3V
Rev.: B
Amendment: /1
1
Issue Date: March, 1999

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