NCV47821
3.3 V to 20 V Adjustable Dual
LDO with Adjustable Current
Limit and Diagnostic Features
The NCV47821 dual channel LDO regulator with 200 mA per
channel is designed for use in harsh automotive environments. The
device has a high peak input voltage tolerance and reverse input voltage,
reverse bias, overcurrent and overtemperature protections. The
integrated current sense feature (adjustable by resistor connected to
CSO pin for each channel) provides diagnosis and system protection
functionality. The CSO pin output current creates voltage drop across
CSO resistor which is proportional to output current of each channel.
Extended diagnostic features in OFF state are also available and
controlled by dedicated input and output pins.
Features
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MARKING
DIAGRAM
14
14
1
TSSOP−14
Exposed Pad
CASE 948AW
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
NCV4
7821
ALYWG
G
•
•
•
•
•
Adjustable Outputs: 3.3 V to 20 V
±3%
Output Voltage
Output Current per Channel: up to 200 mA
Two Independent Enable Inputs (3.3 V Logic Compatible)
Adjustable Current Limits: up to 300 mA
Protection Features:
♦
Current Limitation
♦
Thermal Shutdown
♦
Reverse Input Voltage and Reverse Bias Voltage
•
Diagnostic Features:
♦
Short To Battery (STB) and Open Load (OL) in OFF State
♦
Internal Components for OFF State Diagnostics
♦
Open Collector Flag Output
•
AEC−Q100 Grade 1 Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
•
Audio and Infotainment System
•
Active Safety System
C
in
1
μF
EN1
ADJ1
CSO1
C
CSO1
Diagnostic Enable Input
To A /D
V
in
V
out1
R
11
C
b1
*
C
out1
10
μF
R
12
R
CSO1
DE
Diagnostic Channel Select Input
NCV47821
(Dual LDO )
EF
1
μF
Error Flag Output (Open Collector)
CS
V
out2
R
21
C
b2
*
C
out2
10
μF
R
22
EN2
GND
ADJ2
CSO2
C
CSO2
1
μF
To A /D
R
CSO2
C
b1
* and C
b2
* are optional for stability with ceramic output capacitors
Figure 1. Application Schematic
(See Application Section for More Details)
©
Semiconductor Components Industries, LLC, 2017
1
January, 2017 − Rev. 2
Publication Order Number:
NCV47821/D
NCV47821
I
PU1
10 mA
IPU1_ON
V
in
I
CSO1
= I
out1
/ 100
VOLTAGE
REFERENCE
V
out1
V
REF 1
V
REF 2
V
REF _OFF
EN1
EN1
R
PD_EN1
780 kΩ
ENABLE
SATURATION
PROTECTION
THERMAL
SHUTDOWN
PASS DEVICE 1
AND
CURRENT MIRROR
+
−
+
V
REF 2
2.55 V
CSO1
OC1_ON
PD1_ON
−
0.95x
V
REF 2
R
PD11
500 kΩ
STB1_OL1_OFF
EN1
EN2
IPU1_ON
IPU2_ON
PD1_ON
PD2_ON
+
−
+
EA1
R
PD12
100 kΩ
V
REF_OFF
DE
CS
R
PD_CS
780 kΩ
V
REF 1
1.265 V
ADJ1
EF
R
PD_DE
780 kΩ DIAGNOSTIC
CONTROL
LOGIC
−
OC1_ON
OC2_ON
STB1_OL1_OFF
STB2_OL2_OFF
I
PU2
10 mA
IPU2_ON
V
in
I
CSO2
= I
out2
/ 100
V
out2
EN2
R
PD_EN2
780 kΩ
ENABLE
SATURATION
PROTECTION
THERMAL
SHUTDOWN
EN2
PASS DEVICE 2
AND
CURRENT MIRROR
+
−
+
V
REF 2
2.55 V
CSO2
OC2_ON
PD2_ON
−
0.95x
V
REF 2
R
PD21
500 kΩ
STB2_OL2_OFF
GND
+
−
+
EA2
R
PD22
100 kΩ
V
REF_OFF
V
REF 1
1.265 V
ADJ2
−
Figure 2. Simplified Block Diagram
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2
NCV47821
1
V in
CSO1
EN1
GND
EN2
CSO2
V in
TSSOP−14 EPAD
(Top View)
EPAD
14
V out1
ADJ1
CS
EF
DE
ADJ2
V out2
Figure 3. Pin Connections
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
TSSOP−14
EPAD
1
2
3
4
5
6
7
8
9
10
11
12
Pin Name
V
in
CSO1
EN1
GND
EN2
CSO2
V
in
V
out2
ADJ2
DE
EF
CS
Description
Power Supply Input for Channel 1 and supply of control circuits of whole chip. At least 4.4 V power
supply must be used for proper IC functionality.
Current Sense Output 1, Current Limit setting and Output Current value information. See Application
Section for more details.
Enable Input 1; low level disables the Channel 1. (Used also for OFF state diagnostics control for
Channel 1)
Power Supply Ground.
Enable Input 2; low level disables the Channel 2. (Used also for OFF state diagnostics control for
Channel 2)
Current Sense Output 2, Current Limit setting and Output Current value information. See Application
Section for more details.
Power Supply Input for Channel 2. Connect to pin 1 or different power supply rail.
Regulated Output Voltage 2.
Adjustable Voltage Setting Input 2. See Application Section for more details.
Diagnostic Enable Input.
Error Flag (Open Collector) Output. Active Low.
Channel Select Input for OFF state diagnostics. Set CS = Low for OFF state diagnostics of Chan-
nel 1. Set CS = High for OFF state diagnostics of Channel 2. Corresponding EN pin has to be used
for diagnostics control (see Application Information section for more details).
Adjustable Voltage Setting Input 1. See Application Section for more details.
Regulated Output Voltage 1.
Exposed Pad is connected to Ground. Connect to GND plane on PCB.
13
14
EPAD
ADJ1
V
out1
EPAD
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NCV47821
Table 2. MAXIMUM RATINGS
Rating
Input Voltage DC
Input Voltage (Note 1)
Load Dump − Suppressed
Enable Input Voltage
ADJ Input Voltage
CSO Voltage
DE, CS and EF Voltages
Output Voltage
Junction Temperature
Storage Temperature
Symbol
V
in
U
s*
−
V
EN1,2
V
ADJ1,2
V
CSO1,2
V
DE
, V
CS
V
EF
V
out1,2
T
J
T
STG
−42
−0.3
−0.3
−0.3
−1
−40
−55
60
45
10
7
7
40
150
150
V
V
V
V
V
°C
°C
Min
−42
Max
45
Unit
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class C according to ISO16750−1.
Table 3. ESD CAPABILITY
(Note 2)
Rating
ESD Capability, Human Body Model
Symbol
ESD
HBM
Min
−2
Max
2
Unit
kV
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JS−001−2010)
Field Induced Charge Device Model ESD characterization is not performed on plastic molded packages with body sizes < 50 mm2 due
to the inability of a small package body to acquire and retain enough charge to meet the minimum CDM discharge current waveform
characteristic defined in JEDEC JS−002−2014.
Table 4. LEAD SOLDERING TEMPERATURE AND MSL
(Note 3)
Rating
Moisture Sensitivity Level
Symbol
MSL
Min
1
Max
Unit
−
3. For more information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
(Note 4)
Rating
Thermal Characteristics (single layer PCB)
Thermal Resistance, Junction−to−Air (Note 5)
Thermal Reference, Junction−to−Lead (Note 5)
Thermal Characteristics (4 layers PCB)
Thermal Resistance, Junction−to−Air (Note 5)
Thermal Reference, Junction−to−Lead (Note 5)
Symbol
R
θJA
R
ψJL
R
θJA
R
ψJL
Value
52
9.0
°C/W
31
10
Unit
°C/W
4. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 645 mm
2
(or 1 in
2
) of 1 oz copper thickness and FR4 PCB substrate. Single layer − according to JEDEC51.3,
4 layers − according to JEDEC51.7
Table 5. RECOMMENDED OPERATING RANGES
Rating
Input Voltage (Note 6)
Nominal Output Voltages
Output Current Limit (Note 7)
Junction Temperature
Current Sense Output (CSO) Capacitor
Symbol
V
in
V
out_nom1,2
I
LIM1,2
T
J
C
CSO1,2
Min
4.4
3.3
10
−40
1
Max
40
20
300
150
4.7
Unit
V
V
mA
°C
mF
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Minimum V
in
= 4.4 V or (V
out1,2
+ 0.5 V), whichever is higher.
7. Corresponding R
CSO1,2
is in range from 25.5 kW down to 850
W.
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NCV47821
Table 6. ELECTRICAL CHARACTERISTICS
V
in
= 13.5 V, V
EN1,2
= 3.3 V, V
DE
= 0 V, R
CSO1,2
= 0
W,
C
CSO1,2
= 1
mF,
C
in
= 1
mF,
C
out1,2
= 10
mF,
Min and Max values are valid for temperature range −40°C
v
T
J
v
+150°C unless noted otherwise and are guaranteed
by test, design or statistical correlation. Typical values are referenced to T
J
= 25°C (Note 8)
Parameter
REGULATOR OUTPUTS
Output Voltage (Accuracy %) (Note 9)
Line Regulation (Note 9)
Load Regulation
Dropout Voltage (Note 10)
DISABLE AND QUIESCENT CURRENTS
Disable Current
Quiescent Current, I
q
= I
in
− (I
out1
+I
out2
)
Quiescent Current, I
q
= I
in
– (I
out1
+I
out2
)
CURRENT LIMIT PROTECTION
Current Limit
PSRR & NOISE
Power Supply Ripple Rejection (Note 11) f = 100 Hz, 0.5 V
p−p1,2
Output Noise Voltage (Note 11)
ENABLE
Enable Input Threshold Voltage
Logic Low (OFF)
Logic High (ON)
Enable Input Current
Turn On Time
from Enable ON to 90 % of V
out
OUTPUT CURRENT SENSE
CSO Voltage Level at Current Limit
CSO Transient Voltage Level
Output Current to CSO Current Ratio
(Note 11, 12)
Output Current to CSO Current Ratio
(Note 12)
CSO Current at no Load Current
V
out1,2
= 0.9 x V
out_nom1,2
,
(V
out_nom1,2
= 5 V) R
CSO1,2
= 1 kW
C
CSO1,2
= 4.7
mF,
R
CSO1,2
= 1 kW
I
out1,2
pulse from 10 mA to 300 mA, tr = 1
ms
V
CSO1,2
= 2 V, I
out1,2
= 1 mA to 10 mA
(V
out_nom1,2
= 5 V)
V
CSO1,2
= 2 V, I
out1,2
= 10 mA to 300 mA
(V
out_nom1,2
= 5 V)
V
CSO1,2
= 0 V, I
out1,2
= 0 mA,
(V
out_nom1,2
= 5 V)
V
CSO_I
lim1,2
V
CSO1,2
−
I
out1,2
/
I
CSO1,2
I
out1,2
/
I
CSO1,2
I
CSO_off1,2
−
(−5%)
−
(−5%)
−
−
98
100
−
3.3
−
(+5%)
−
(+5%)
10
−
−
mA
2.448
(−4%)
2.55
2.652
(+4%)
V
V
V
out1,2
v
0.1 V
V
out1,2
w
0.9 x V
out_nom1,2
(V
out_nom1,2
= 5 V)
V
EN1,2
= 3.3 V, V
out_nom1,2
= 5 V
I
out1,2
= 100 mA, C
b1,2
= 10 nF,
R
n1
= 82 kW, R
n2
= 27 kW
V
th(EN1,2)
0.99
−
I
EN1,2
t
on
−
1.7
−
2
1.8
1.9
8
−
2.31
20
mA
ms
V
f = 10 Hz to 100 kHz, C
b1,2
= 10 nF
PSRR
1,2
V
n1,2
−
−
75
137
−
−
dB
mV
rms
V
out1,2 =
0.9 x V
out_nom1,2
V
in
= (V
out_nom1,2
+ 8.5 V)
I
LIM1,2
300
−
−
mA
V
EN1,2
= 0 V, V
out_nom1,2
= 5 V,
−40°C
v
T
J
v
+125°C
I
out1
= I
out2
= 500
mA,
V
in
= (V
out_nom
+ 8.5 V)
I
out1
= I
out2
= 200 mA, V
in
= (V
out_nom
+ 8.5 V)
Test Conditions
Symbol
Min
Typ
Max
Unit
V
in
= V
in_min
to 40 V
I
out1,2
= 5 mA to 200 mA
V
in
= V
in_min
to (V
out_nom1,2
+ 20 V)
I
out1,2
= 5 mA
V
in
= (V
out_nom1,2
+ 8.5 V)
I
out1,2
= 5 mA to 200 mA
V
out_nom1,2
= 5 V, I
out1,2
= 200 mA
V
DO1,2
= V
in
− V
out1,2
V
out1,2
−3
Reg
line1,2
−
Reg
load1,2
−
V
DO1,2
−
0.4
250
1.4
500
0.1
1.0
−
+3
%
%
%
mV
I
DIS
I
q
I
q
−
−
−
0.1
0.6
15.5
10
1.0
25
mA
mA
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T
A
[
T
J
. Low duty
cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
9. Minimum input voltage V
in_min
is 4.4 V or (V
out_nom1,2
+ 1 V) whichever is higher. V
out_nom1,2
measured at ADJ1,2 pin due to excluding
R
n1
and R
n2
accuracy.
10. Measured when the output voltage V
out1,2
has dropped by 2% of V
out_nom1,2
from the nominal valued obtained at V
in
= V
out1,2
+ 8.5 V.
11. Values based on design and/or characterization.
12. Not guaranteed in dropout.
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