NCV7428
System Basis Chip with
Integrated LIN and Voltage
Regulator
Description
NCV7428 is a System Basis Chip (SBC) integrating functions
typically found in automotive Electronic Control Units (ECUs).
NCV7428 provides and monitors the low−voltage power supply for
the application microcontroller and other loads and includes a LIN
transceiver.
Features
♦
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8
1
SOIC−8
D SUFFIX
CASE 751AZ
1
DFN8
MW SUFFIX
CASE 506DG
•
Control Logic
•
•
•
•
Ensures safe power−up sequence and the correct reaction to
different supply conditions
♦
Controls mode transitions including the power management and
bus wakeup treatment
♦
Generates reset
3.3 V or 5 V V
OUT
Supply depending on the Version from a
Low−drop Voltage Regulator
♦
Can deliver up to 70 mA with accuracy of
±2%
♦
Supplies typically the ECU’s microcontroller
♦
Undervoltage detector with a reset output to the supplied
microcontroller
LIN Transceiver
♦
LIN2.x and J2602 compliant
♦
TxD dominant timeout protection
♦
Transceiver mode controlled by dedicated input pin
Protection and Monitoring Functions
♦
Thermal shutdown protection
♦
Load dump protection (45 V)
♦
LIN Bus pin protected against transients in an automotive
environment
♦
ESD protection level for LIN and V
S
>
±8
kV
Wettable Flank Package for Enhanced Optical Inspection
MARKING DIAGRAMS
8
NV7428xx
ALYW
G
G
1
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
1
NV7428xx
ALYWG
G
(Note: Microdot may be in either location)
PIN ASSIGNMENT
1
V
S
EN
GND
4
LIN
(Top View)
2
3
7
6
5
NCV7428
8
V
OUT
RSTN
TxD
RxD
Quality
•
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 17 of this data sheet.
•
Automotive
•
Industrial Networks
©
Semiconductor Components Industries, LLC, 2016
November, 2018
−
Rev. 7
1
Publication Order Number:
NCV7428/D
NCV7428
Block Diagram
V
OUT
V
S
NCV7428
REF
V−reg
OSC
V
OUT
V
OUT
V
S
RSTN
Undervoltage
Detection
Thermal
Shutdown
Control Logic
EN
V
S
V
OUT
Wakeup
Detection
LIN Wakeup
RxD
LIN Active
Receiver
LIN
V
OUT
Driver &
Slope
Control
TxD
Timeout
GND
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
EP
NOTE:
Pin Name
V
S
EN
GND
LIN
RxD
TxD
RSTN
V
OUT
EP
Pin Type
Battery supply input
LV LIN enable input;
internal pull−down
Ground connection
LIN bus interface
LV digital output; push−pull
LV digital input; internal pull−up
LV digital output;
open drain; internal pull−up
LV supply output
Exposed Pad
Pin Function
Principle power supply of the device
Input of the LIN block enable signal
Ground connection
LIN bus line
Output of data received on LIN bus
Input of the data to be transmitted from LIN bus
System reset
Output of the 5 V or 3.3 V/70 mA low−drop regulator (for the MCU)
Connect to GND or leave floating
(LV = Low Voltage; HV = High Voltage)
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NCV7428
Application Information
ECU1
(MASTER)
VBAT
D
REV
C
VS
R
PU_RSTN
C
VOUT
ECU2
(SLAVE)
VBAT
D
REV
C
VS
R
PU_RSTN
C
VOUT
V
CC
V
S
V
OUT
RSTN
EN
TxD
RxD
V
CC
D
PU_LIN
R
PU_LIN
V
S
V
OUT
RSTN
EN
TxD
RxD
GND
NCV7428
NCV7428
LIN
C
LIN_M
MCU
LIN
LIN
C
LIN_S
MCU
LIN
GND
GND
GND
GND
GND
KL30
LIN−BUS
KL31
Figure 2. Example Application Diagram
External Components
Overview of external components from application schematic in Figure 2 is given in Table 2 together with their recommended
or required values.
Table 2. EXTERNAL COMPONENTS OVERVIEW
Component
Name
D
REV
C
VS
C
VOUT
D
PU_LIN
R
PU_LIN
C
LIN_M
C
LIN_S
R
PU_RSTN
Description
Reverse polarity protection diode
Filtering capacitor for the battery input
Voltage regulator output filtering and
stabilization capacitor
Master node Pull−up diode on LIN line
Master node Pull−up resistor on LIN line
Filtering capacitor on LIN line (Master node)
Filtering capacitor on LIN line (Slave node)
Pull−up resistor at RSTN pin
1 kW nominal,
≥500
mW
typically 1 nF
typically 100 pF – 220 pF
recommended 10 kW nominal
Value
parameters application−specific;
e.g. 0.5 A / 50 V
recommended >100 nF ceramic
> 1.8
mF,
ESR < 7
W
required only for master
LIN node
optional; is function of the
entire LIN network
optional; is function of the
entire LIN network
optional; depends on
application needs
Note
required values and types
depend on the V
OUT
load
and the application needs
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NCV7428
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
V
S
V
OUT
V
LIN
V
Dig_IO_inputs
V
Dig_IO_outputs
T
AMB
T
J
T
STG
V
ESD
Maximum DC voltage at V
S
pin
Maximum voltage at V
OUT
pin
Maximum voltage at LIN bus pin
Maximum voltage at digital input pins (TxD, EN)
Maximum voltage at digital output pins (RxD, RSTN)
Ambient temperature range
Junction temperature range
Storage temperature range
System ESD at pins VS, LIN as per IEC 61000−4−2: 330
W
/ 150 pF
(Verified by external test house)
Human body model at pins VS, LIN stressed towards GND with 1500
W
/ 100 pF
Human body model at all pins as per JESD22−A114 / AEC−Q100−002
Charge device model at all pins as per JESD22−C101 / AEC−Q100−011
Machine model; (200 pF; 0.75
mH;
10
W)
as per JESD22−A115 / AEC−Q100−003
MSL
T
SLD
Moisture Sensitivity Level
Lead temperature Soldering
−
Reflow (SMD styles only), Pb−Free (Note 1)
SOIC
DFN
Parameter
Min
−0.3
−0.3
−45
−0.3
−0.3
−40
−40
−55
Max
45
6
45
45
V
OUT
+0.3
+125
+170
+150
≥
±14
≥
±8
≥
±4
≥
±500
±200
2
1
260
Units
V
V
V
V
V
°C
°C
°C
kV
kV
kV
V
V
−
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 4. OPERATING RANGES
Symbol
V
S
V
OUT5
V
OUT33
I
VOUT
V
LIN
V
Dig_IO_inputs
V
Dig_IO_outputs
Parameter
VS operating voltage for parametric operation (Note 2)
VS operating voltage for limited operation (Note 2)
Regulated voltage at V
OUT
supply output for 5 V versions
Regulated voltage at V
OUT
supply output for 3.3 V versions
Current delivered by the V
OUT
regulator
Operating voltage at LIN bus pin
Operating voltage at digital input pins (TxD, EN)
Operating voltage at digital output pins (RxD, RSTN)
Min
5.5
4
4.9
3.234
70
0
0
0
V
S
5.5
V
OUT
Max
28
28
5.1
3.366
Units
V
V
V
V
mA
V
V
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. Below 5.5 V at V
S
pin in normal mode, the bus will either stay recessive or comply with the voltage level specifications and transition time
specifications as required by SAE J2602. It is ensured by the battery monitoring circuit. Above 28 V at V
S
pin, LIN communication is
operational (LIN pin toggling) but parameters cannot be guaranteed. For higher battery voltage operation above 28 V, LIN pull−up resistor
must be selected large enough to avoid clamping of LIN pin by voltage drop over external pull−up resistor and LIN pin min current limitation.
Table 5. THERMAL CHARACTERISTICS
Rating
Thermal Characteristics, SOIC−8 (Note 3)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 4)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 5)
Thermal Characteristics, DFN−8 (Note 3)
Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 4)
Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 5)
Symbol
R
qJA
R
qJA
R
qJA
R
qJA
Value
125
75
133
55
Unit
°C/W
°C/W
°C/W
°C/W
3. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
4. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage.
5. Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage for the signal layer and
4 thermal vias connected between exposed pad and first inner Cu layer.
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NCV7428
Definitions
The characteristics defined in this section are guaranteed within the operating ranges listed in Table 4, unless stated
otherwise. All voltages are referenced to GND (Pin 3). Positive currents flow into the respective pin.
Table 6. DC CHARACTERISTICS
(V
S
= 5.5 V to 28 V; T
J
=
−40°C
to +150°C; Bus Load = 500
W
(V
S
to LIN); unless otherwise
specified. Typical values are given at V
S
= 12 V and T
J
= 25°C, unless otherwise specified.)
Symbol
SUPPLY MONITORING
V
S_PORH
V
S_PORL
V
OUT_RES_5
V
OUT_RES_33
V
OUT_RES_hys5
V
OUT_RES_hys33
V
S
threshold for the power−up
of the circuit
V
S
threshold for the Shutdown
of the circuit
V
OUT
monitoring threshold
NV7428−5
V
OUT
monitoring threshold
NV7428−3
V
OUT
monitoring threshold
hysteresis for NV7428−5
V
OUT
monitoring threshold
hysteresis for NV7428−3
V
S
rising
V
S
falling
V
OUT
falling
V
OUT
falling
3.3
2.2
4.55
2.97
0.1
0.06
4
3
4.75
3.135
V
V
V
V
V
V
Parameter
Conditions
Min
Typ
Max
Unit
CURRENT CONSUMPTION
I
VS_LIN_Active_rec
I
VS_LIN_Wakeup
V
S
supply current
V
S
supply current (Note 8)
LIN Active, LIN bus recessive
Standby mode; LIN Wakeup,
LIN bus recessive; I
VOUT
= 0 mA
V
S
= 13.5 V, T
J
< 105°C
Sleep mode; LIN Wakeup, LIN bus
recessive; V
OUT
off, V
OUT
< 0.5 V
V
S
= 13.5 V, T
J
< 105°C
V
OUT
regulator active,
0 < I
VOUT
< 70 mA, Static
regulation, V
S
= 5.5 V to 28 V
V
OUT
regulator active,
0 < I
VOUT
< 70 mA, Static
regulation, V
S
= 4.5 V to 28 V
DPI EMC test applied to LIN pin.
No bus capacitor. SOIC8 package;
(Note 7)
DPI EMC test applied to LIN pin.
No bus capacitor. SOIC8 package;
(Note 7)
V
OUT
regulator active;
current flowing to V
OUT
load
5.5 V < V
S
< 40 V;
I
VOUT
= 70 mA
V
OUT
regulator active, current
flowing into the V
OUT
pin
Equivalent series resistance < 7
W
100
1.8
240
10
4.9
25
1.8
33
mA
mA
I
VS_Sleep
V
S
supply current (Note 8)
12
18
mA
V
OUT
REGULATOR
V
OUT_5
V
OUT
regulator output voltage
(Note 6)
V
OUT
regulator output voltage
(Note 6)
V
OUT
regulator output voltage
under EMC (Note 8)
V
OUT
regulator output voltage
under EMC (Note 8)
V
OUT
current limitation
Drop−out voltage between V
S
and V
OUT
V
OUT
sink current
V
OUT
regulator filtering
capacitance (Note 9)
5
5.1
V
V
OUT_33
3.234
3.3
3.366
V
V
OUT_5_EMC
4.85
5
5.15
V
V
OUT_33_EMC
3.201
3.3
3.399
V
I
LIM_VOUT
V
DROP_VOUT
I
SINK_VOUT
C
VOUT
70
120
350
0.55
400
mA
V
mA
mF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. In case LIN bus capacitor of at least 82 pF is not used V
OUT_5_EMC
and V
OUT_33_EMC
needs to be taken into account.
7. Tested according to: LIN Conformance Test Specification Package for LIN 2.1, October 10
th
, 2008. Verified by external test house.
8. Values based on design and characterization. Not tested in production.
9. In parallel with this capacitor any other capacitor can be placed with no limit to ESR and capacitance value
10. The voltage drop in Normal mode between LIN and V
S
pin is the sum of the diode drop and the drop at serial pull−up resistor. The drop
at the switch is negligible. See Figure 1.
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