RHYTHM SA3229
Preconfigured DSP System
for Hearings Aids
Description
The RHYTHMt SA3229 hybrid from ON Semiconductor is
a trimmer−configurable DSP system based on a four−channel
compression circuit featuring a feedback cancellation algorithm.
Based on a phase cancellation method, SA3229’s adaptive feedback
reduction algorithm provides added stable gain to enable extra gain
and user comfort. It features rapid adjustment for dynamic feedback
situations and resistance to tonal inputs.
In addition to these adaptive algorithms, SA3229 also supports the
following features: up to four channel WDRC, low−distortion
compression limiting, cross fading between audio paths for click−free
memory changes, eight−band graphic equalizer, eight configurable
generic biquad filters, programming speed enhancements, in−channel
squelch to attenuate microphone and circuit noise in quiet
environments, optional peak clipping, flexible compression
adjustments, volume control, rocker switch, noise generation for
Tinnitus treatment, and industry−leading security features to avoid
cloning and software piracy.
A trimmer interface supports manual circuit configuration. It
continuously monitors trimmer positions and translates them into
the hearing−aid parameters of choice. A Serial Data or I
2
C Interface
provides full programmability at the factory and in the field.
RHYTHM SA3229 is a single−chip hybrid with a one−time
programmable (OTP) memory intended for low cost applications
requiring high gain.
Features
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SIP25
HYBRID
CASE 127DZ
PAD CONNECTION
18
VIN1
19
TR4
20
TR3
21
TR2
22
TR1
23
N/C
N/C
N/C
25
24
VIN2
TIN
DAI
VC
D_VC
SDA
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
VREG
MGND
GND
PGND
OUT+
OUT−
VBP
•
Adaptive Feedback Cancellation
•
WDRC Compression with Choice of 1, 2 or 4 Channels of
•
•
•
•
•
•
•
•
•
•
•
•
Compression
Auto Telecoil with Programmable Delay
EVOKE LITEt Acoustic Indicators
Noise Generator for Tinnitus Treatment or In−Situ Audiometry
Frequency Response Shaping with Graphic EQ
Trimmer Compatibility – Four Three−Terminal Trimmers with
Configurable Assignments of Control Parameters
I
2
C and SDA Programming
Rocker Switch Support for Memory Change and/or Volume Control
Adjustment
Support for Active High or Active Low Switching
Analog or Digital Volume Control with Programmable Range
High Quality 20−bit Audio Processing
High Power/High Gain Capability
Configurable Low Battery Indicator
CLK
MS1
9
MS2
(Bottom View)
VB
MARKING DIAGRAM
SA3229−E1
XXXXXX
SA3229 = Specific Device Code
E1
= RoHS Compliant Hybrid
XXXXXX = Work Order Number
ORDERING INFORMATION
See detailed ordering and shipping information on page 13 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2017
1
February, 2017 − Rev. 1
Publication Order Number:
SA3229/D
RHYTHM SA3229
•
Eight Biquadratic Filters
•
16 kHz or 8 kHz Bandwidth
•
Four Fully Configurable Memories with Audible
Memory Change Indicator
•
96 dB Input Dynamic Range with HRX Headroom
Extension
•
128−bit Fingerprint Security System and Other Security
Features to Protect Against Device Cloning and
Software Piracy
•
•
•
•
•
High Fidelity Audio CODEC
Soft Acoustic Fade between Memory Changes
Drives Zero−Bias Two−Terminal Receivers
E1 RoHS−compliant Hybrid
Hybrid Typical Dimensions:
0.225 x 0.125 x 0.045 in
(5.72 x 3.18 x 1.14 mm)
•
These Devices are Pb−Free and are RoHS Compliant
BLOCK DIAGRAM
MS2
9
MS1
10
SDA
12
CLK
11
VB
8
PROGRAMMING
INTERFACE
VREG
1
REGULATOR
FEEDBACK
CANCELLER
TONE
GENERATOR
7
VBP
OUT+
OUT −
PGND
MIC1
MIC2
TIN
DAI
18
A/D
+
MIC / TELECOIL
COMPENSATION
PRE BIQUAD FILTERS
1−4
POST BIQUAD FILTERS
3&4
17
16
15
CROSS
FADER
PEAK
CLIPPING
D/A
HBRIDGE
5
6
A/D
1, 2 or 4 CHANNEL
WDRC
POST BIQUAD FILTERS
1&2
AGC−O
EVOKE
VC GAIN
WIDEBAND GAIN
4
MGND
2
TRIMMER/VC INTERFACE
NOISE GENERATOR
19
BIQUAD 1−4
3
SA3229
13
14
22
21
20
D_VC
VC
TR1
TR2
TR3
TR4
GND
Figure 1. Hybrid Block Diagram
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2
RHYTHM SA3229
SPECIFICATIONS
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature Range
Storage Temperature Range
Absolute Maximum Power Dissipation
Maximum Operating Supply Voltage
Absolute Maximum Supply Voltage
Value
0 to +40
−20 to +70
25
1.65
1.8
Units
°C
°C
mW
VDC
VDC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
WARNING:
Electrostatic Sensitive Device − Do not open packages or handle except at a static−free workstation.
WARNING:
Moisture Sensitive Device − RoHS Compliant; Level 4 MSL. Do not open packages except under controlled conditions.
Table 2. ELECTRICAL CHARACTERISTICS
(Supply Voltage V
B
= 1.25 V; Temperature = 25°C)
Parameter
Hybrid Current
Symbol
I
AMP
Conditions
All functions, 32 kHz sampling rate
All functions, 16 kHz sampling rate
Minimum Operating Supply Voltage
V
BOFF
Ramp down, audio path
Ramp down, control logic
Supply Voltage Turn On Threshold
Low Frequency System Limit
High Frequency System Limit
Total Harmonic Distortion
THD at Maximum Input
Clock Frequency
Audio Path Latency
V
BON
−
−
THD
THD
M
f
CLK
−
−
System Power On Time (Note 1)
REGULATOR
Regulator Voltage
System PSRR
INPUT
Input Referred Noise
Input Impedance
Anti−aliasing Filter Rejection
Crosstalk
Maximum Input Level
Analogue Input Voltage Range
IRN
Z
IN
−
−
−
V
AN_IN
V
AN_TIN
Input Dynamic Range
−
Bandwidth 100 Hz − 8 kHz, HRX on
1 kHz
f
=
f
CLK/2
− 8 kHz, V
IN
= −40 dBV
Between both A/D and Mux
−
V
IN1
, V
IN2
, Al
T
IN
HRX − ON Bandwidth
100 Hz − 8 kHz
−
−
−
−
−15
0
−100
−
−108
3
80
60
−13
−
−
95
−106
−
−
−
−
800
800
96
dB
dBV
MW
dB
dB
dBV
mV
V
REG
PSRR
SYS
−
1 kHz, Input referred, HRX enabled
0.87
−
0.90
70
0.93
−
V
dB
−
Ramp up
−
−
V
IN
= −40 dBV
V
IN
= −15 dBV, HRX − ON
−
8 kHz bandwidth
16 kHz bandwidth
SA3229
Min
−
−
0.93
0.77
1.06
−
−
−
−
3.973
−
−
−
Typ
640
535
0.95
0.80
1.10
125
16
−
−
4.096
4.2
4.0
700
Max
−
−
0.97
0.83
1.16
−
−
1
3
4.218
−
−
−
ms
V
Hz
kHz
%
%
MHz
ms
V
Units
mA
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RHYTHM SA3229
Table 2. ELECTRICAL CHARACTERISTICS
(Supply Voltage V
B
= 1.25 V; Temperature = 25°C) (continued)
Parameter
OUTPUT
D/A Dynamic Range
Output Impedance
CONTROL A/D
Resolution (monotonic)
Zero Scale Level
Full Scale Level
VOLUME CONTROL
Volume Control Resistance
Volume Control Range
PC_SDA INPUT
Logic 0 Voltage
Logic 1 Voltage
PC_SDA OUTPUT
Stand−by Pull Up Current
Sync Pull Up Current
Max Sync Pull Up Current
Min Sync Pull Up Current
Logic 0 Current (Pull Down)
Logic 1 Current (Pull Up)
Synchronization Time
(Synchronization Pulse Width)
−
−
−
−
−
−
T
SYNC
Creftrim = 6
Creftrim = 6
Creftrim = 15
Creftrim = 0
Creftrim = 6
Creftrim = 6
Baud = 0
Baud = 1
Baud = 2
Baud = 3
Baud = 4
Baud = 5
Baud = 6
Baud = 7
3
748
−
−
374
374
237
118
59
29.76
14.88
7.44
3.72
1.86
5
880
1380
550
440
440
250
125
62.5
31.25
15.63
7.81
3.91
1.95
6.5
1020
−
−
506
506
263
132
66
32.81
16.41
8.20
4.10
2.05
mA
mA
mA
mA
mA
mA
ms
−
−
−
−
0
1
−
−
0.3
1.25
V
V
R
VC
−
Three−terminal connection
−
100
−
−
−
360
42
kW
dB
−
−
−
−
−
−
7
−
−
−
0
V
REG
−
−
−
bits
V
V
−
Z
OUT
100 Hz − 8 kHz
−
−
−
88
10
−
13
dB
W
Symbol
Conditions
Min
Typ
Max
Units
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Times do not include additional programmable startup delay.
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4
RHYTHM SA3229
Table 3. I
2
C TIMING
Standard Mode
Parameter
Clock Frequency
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
LOW Period of the PC_CLK Clock
HIGH Period of the PC_CLK Clock
Set−up time for a repeated START condition
Data Hold Time:
for CBUS Compatible Masters
for I
2
C−bus Devices
Data set−up time
Rise time of both PC_SDA and PC_CLK signals
Fall time of both PC_SDA and PC_CLK signals
Set−up time for STOP condition
Bus free time between a STOP and START condition
Output fall time from V
IHmin
to V
ILmax
with a bus
capacitance from 10 pF to 400 pF
Pulse width of spikes which must be suppressed by
the input filter
Capacitive load for each bus line
Symbol
f
PC_CLK
t
HD;STA
t
LOW
t
HIGH
t
SU;STA
t
HD;DAT
5.0
0
(Note 1)
t
SU;DAT
t
r
t
f
t
SU;STO
t
BUF
t
of
t
SP
C
b
250
−
−
4.0
4.7
−
n/a
−
−
3.4
(Note 2)
−
1000
300
−
−
250
n/a
400
−
0
(Note 1)
100
20 + 0.1 C
b
(Note 4)
20 + 0.1 C
b
(Note 4)
0.6
1.3
20 + 0.1 C
b
(Note 4)
0
−
−
0.9
(Note 2)
−
300
300
−
−
250
50
400
nsec
nsec
nsec
nsec
msec
nsec
nsec
pF
Min
0
4.0
4.7
4.0
4.7
Max
100
−
−
−
−
Fast Mode
Min
0
0.6
−
−
−
Max
400
−
−
−
−
Units
kHz
msec
msec
msec
msec
msec
1. A device must internally provide a hold time of at least 300 ns for the PC_SDA signal to bridge the undefined region of the falling edge of PC_CLK.
2. The maximum t
HD;DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the PC_CLK signal.
3. A Fast−mode I
2
C−bus device can be used in a Standard−mode I
2
C−bus system, but the requirement t
SU;DAT
P250ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the PC_CLK signal. If such a device does stretch the
LOW period of the PC_CLK signal, it must output the next data bit to the PC_SDA line t
r
max + t
SU;DAT
= 1000 + 250 = 1250 ns (according
to the Standard−mode I
2
C−bus specification) before the PC_CLK line is released.
4. C
b
= total capacitance of one bus line in pF.
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