MC74VHC1GT02
Single 2-Input NOR Gate/
CMOS Logic Level Shifter
LSTTL−Compatible Inputs
The MC74VHC1GT02 is a single gate 2−input NOR fabricated with
silicon gate CMOS technology.
The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT02 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT02 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
V
CC
= 0 V. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
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MARKING
DIAGRAMS
5
1
SC−88A/SC70−5/SOT−353
DF SUFFIX
CASE 419A
5
VJ M
G
G
M
1
5
5
1
TSOP−5/SOT23−5/SC59−5
DT SUFFIX
CASE 483
VJ M
G
G
1
•
•
•
•
•
•
•
•
•
High Speed: t
PD
= 4.7 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 1
mA
(Max) at T
A
= 25°C
TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2 V
CMOS−Compatible Outputs: V
OH
> 0.8 V
CC
; V
OL
< 0.1 V
CC
@Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
VJ = Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
PIN ASSIGNMENT
1
2
3
4
5
IN B
IN A
GND
OUT Y
V
CC
Chip Complexity: FETs = 65
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free and are RoHS Compliant
IN B 1
5
V
CC
FUNCTION TABLE
Inputs
Output
B
L
H
L
H
Y
H
L
L
L
IN A 2
GND
3
A
L
L
H
H
4
OUT Y
Figure 1. Pinout
IN A
IN B
≥
1
OUT Y
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
©
Semiconductor Components Industries, LLC, 2015
1
November, 2015 − Rev. 12
Publication Order Number:
MC74VHC1GT02/D
MC74VHC1GT02
MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
DC Supply Current, V
CC
and GND
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 28 to 34
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Above V
CC
and Below GND at 125_C (Note 5)
SC70−5/SC−88A/SOT−353 (Note 1)
SOT23−5/TSOP−5/SC59−5
SC70−5/SC−88A/SOT−353
SOT23−5/TSOP−5/SC59−5
V
OUT
< GND; V
OUT
> V
CC
V
CC
= 0
High or Low State
Characteristics
Value
−0.5 to +7.0
−0.5 to +7.0
−0.5 to 7.0
−0.5 to V
CC
+ 0.5
−20
+20
+25
+50
*65
to
)150
260
)150
350
230
150
200
Level 1
UL 94 V−0 @ 0.125 in
u2000
u200
N/A
$500
V
Unit
V
V
V
mA
mA
mA
mA
_C
_C
_C
_C/W
mW
I
LATCHUP
Latchup Performance
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature Range
Input Rise and Fall Time
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5.0 V
±
0.5 V
V
CC
= 0
High or Low State
Characteristics
Min
3.0
0.0
0.0
0.0
−55
0
0
Max
5.5
5.5
5.5
V
CC
+125
100
20
Unit
V
V
V
°C
ns/V
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature
°C
80
90
100
110
120
130
140
Time, Hours
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
Time, Years
117.8
47.9
20.4
9.4
4.2
2.0
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
T
J
= 130_C
T
J
= 120_C
T
J
= 100_C
T
J
= 110_C
T
J
= 90_C
T
J
= 80_C
100
TIME, YEARS
1
1
10
1000
Figure 3. Failure Rate vs. Time Junction Temperature
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MC74VHC1GT02
DC ELECTRICAL CHARACTERISTICS
V
CC
Symbol
V
IH
Parameter
Minimum High−Level
Input Voltage
Maximum Low−Level
Input Voltage
Minimum High−Level
Output Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
= −50
mA
V
IN
= V
IH
or V
IL
I
OH
= −4 mA
I
OH
= −8 mA
V
IN
= V
IH
or V
IL
I
OL
= 50
mA
V
IN
= V
IH
or V
IL
I
OL
= 4 mA
I
OL
= 8 mA
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND
Per Input: V
IN
= 3.4 V
Other Input: V
CC
or
GND
V
OUT
= 5.5 V
Test Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
3.0
4.5
3.0
4.5
3.0
4.5
0 to
5.5
5.5
5.5
2.9
4.4
2.58
3.94
0.0
0.0
0.1
0.1
0.36
0.36
±0.1
1.0
1.35
3.0
4.5
Min
1.4
2.0
2.0
0.53
0.8
0.8
2.9
4.4
2.48
3.80
0.1
0.1
0.44
0.44
±1.0
20
1.50
T
A
= 25°C
Typ
Max
T
A
≤
85°C
Min
1.4
2.0
2.0
0.53
0.8
0.8
2.9
4.4
2.34
3.66
0.1
0.1
0.52
0.52
±1.0
40
1.65
mA
mA
mA
V
V
Max
−55
≤
T
A
≤
125°C
Min
1.4
2.0
2.0
0.53
0.8
0.8
Max
Unit
V
V
IL
V
V
OH
V
V
V
OL
Maximum Low−Level
Output Voltage
V
IN
= V
IH
or V
IL
I
IN
I
CC
I
CCT
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
Quiescent Supply
Current
Power Off Output
Leakage Current
I
OFF
0.0
0.5
5.0
10
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎ Î Î Î
Î
Î
ÎÎ Î Î ÎÎ Î Î Î
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î ÎÎ Î Î Î
Î
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎ Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎ Î Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎ Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎ Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎ Î Î Î
Î
Î
Î Î Î ÎÎ Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î ÎÎ Î Î Î
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS
Input t
r
= t
f
= 3.0 ns
T
A
= 25°C
Typ
4.5
5.8
3.0
3.8
5.5
T
A
≤
85°C
−55
≤
T
A
≤
125°C
Min
Max
Symbol
t
PLH
,
t
PHL
Parameter
Test Conditions
Min
Max
Min
Max
Unit
ns
Maximum Propagation
Delay, Input A or B to Y
V
CC
= 3.3
±
0.3 V
V
CC
= 5.0
±
0.5 V
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
10.0
13.5
6.7
7.7
10
11.0
15.0
7.5
8.5
10
13.0
17.5
8.5
9.5
10
C
IN
Maximum Input
Capacitance
pF
Typical @ 25°C, V
CC
= 5.0 V
11
C
PD
Power Dissipation Capacitance (Note 6)
pF
6. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
. C
PD
is used to determine the no−load dynamic
power consumption; P
D
= C
PD
V
CC2
f
in
+ I
CC
V
CC
.
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3
MC74VHC1GT02
A or B
50%
GND
t
PLH
Y
50% V
CC
V
OL
t
PHL
V
OH
3.0 V
Figure 4. Switching Waveforms
TEST POINT
INPUT
OUTPUT
C
L
*
*Includes all probe and jig capacitance
Figure 5. Test Circuit
ORDERING INFORMATION
Device
M74VHC1GT02DFT1G
M74VHC1GT02DFT2G
NLVVHC1GT02DFT2G*
M74VHC1GT02DTT1G
NLV74VHC1GT02DTT1G*
SOT23−5/TSOP−5/SC59−5
(Pb−Free)
SC70−5/SC−88A/SOT−353
(Pb−Free)
3000 / Tape & Reel
Package
Shipping
†
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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4
MC74VHC1GT02
PACKAGE DIMENSIONS
SC−88A, SOT−353, SC−70
CASE 419A−02
ISSUE L
A
G
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
S
1
2
3
−B−
DIM
A
B
C
D
G
H
J
K
N
S
D
5 PL
0.2 (0.008)
M
B
M
N
J
C
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
---
0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
---
0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
H
K
SOLDER FOOTPRINT
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
mm
inches
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