Lead Temperature (Soldering, 10 sec) .................. 300°C
Storage Temperature Range................... –65°C to 150°C
(DD Package) ..................................... –65°C to 125°C
Operating Temperature Range
C Grade ................................................... 0°C to 70°C
I Grade ............................................... –40°C to 85°C
PIN CONFIGURATION
TOP VIEW
+IN A
–IN A
–IN B
+IN B
1
2
3
4
9
8
7
6
5
V
CC
OUT A
OUT B
GND
+IN A
–IN A
–IN B
+IN B
1
2
3
4
TOP VIEW
8
7
6
5
V
CC
OUT A
OUT B
GND
DD PACKAGE
8-LEAD (3mm 3mm) PLASTIC DFN
T
JMAX
= 125°C,
θ
JA
= 160°C/W
UNDERSIDE METAL INTERNALLY
CONNECTED TO GND
MS8 PACKAGE
8-LEAD PLASTIC MSOP
T
JMAX
= 150°C,
θ
JA
= 230°C/W
TOP VIEW
–IN A
TOP VIEW
+IN A 1
–IN A 2
–IN B 3
+IN B 4
8
7
6
5
V
CC
OUT A
OUT B
GND
+IN A
GND
OUT A
OUT B
GND
+IN B
–IN B
1
2
3
4
5
6
7
8
16 –IN D
15 +IN D
14 V
CC
13 OUT D
12 OUT C
11 V
CC
10 +IN C
9
–IN C
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 150°C,
θ
JA
= 200°C/W
GN PACKAGE
16-LEAD NARROW
PLASTIC SSOP
S PACKAGE
16-LEAD PLASTIC SO
T
JMAX
= 150°C,
θ
JA
= 135°C/W (GN)
T
JMAX
= 150°C,
θ
JA
= 115°C/W (S)
17201fc
2
LT1720/LT1721
ORDER INFORMATION
LEAD FREE FINISH
LT1720CDD#PBF
LT1720IDD#PBF
LT1720CMS8#PBF
LT1720IMS8#PBF
LT1720CS8#PBF
LT1720IS8#PBF
LT1721CGN#PBF
LT1721IGN#PBF
LT1721CS#PBF
LT1721IS#PBF
TAPE AND REEL
LT1720CDD#TRPBF
LT1720IDD#TRPBF
LT1720CMS8#TRPBF
LT1720IMS8#TRPBF
LT1720CS8#TRPBF
LT1720IS8#TRPBF
LT1721CGN#TRPBF
LT1721IGN#TRPBF
LT1721CS#TRPBF
LT1721IS#TRPBF
PART MARKING*
LAAV
LAAV
LTDS
LTACW
1720
1720I
1721
1721I
1721
1721I
PACKAGE DESCRIPTION
8-Lead (3mm
×
3mm) Plastic DFN
8-Lead (3mm
×
3mm) Plastic DFN
8-Lead Plastic MSOP
8-Lead Plastic MSOP
8-Lead Plastic SO
8-Lead Plastic SO
16-Lead Narrow Plastic SSOP
16-Lead Narrow Plastic SSOP
16-Lead Plastic SO
16-Lead Plastic SO
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
The
l
denotes specifications that apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
CC
= 5V, V
CM
= 1V, C
OUT
= 10pF V
OVERDRIVE
= 20mV, unless otherwise specified.
,
SYMBOL
V
CC
I
CC
V
CMR
V
TRIP+
V
TRIP–
V
OS
V
HYST
ΔV
OS
/ΔT
I
B
I
OS
CMRR
PSRR
A
V
V
OH
V
OL
t
PD20
t
PD5
PARAMETER
Supply Voltage
Supply Current (Per Comparator)
Common Mode Voltage Range
Input Trip Points
Input Trip Points
Input Offset Voltage
Input Hysteresis Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Voltage Gain
Output High Voltage
Output Low Voltage
Propagation Delay
Propagation Delay
(Note 4)
(Note 5)
(Note 6)
I
SOURCE
= 4mA, V
IN
= V
TRIP+
+ 10mV
I
SINK
= 10mA, V
IN
= V
TRIP–
– 10mV
V
OVERDRIVE
= 20mV (Note 7)
V
OVERDRIVE
= 5mV (Notes 7, 8)
l
l
l
l
ELECTRICAL CHARACTERISTICS
CONDITIONS
l
MIN
2.7
l
l
l
l
l
l
l
l
l
l
l
l
TYP
4
3.5
MAX
6
7
6
V
CC
– 1.2
5.5
6.5
2.0
3.0
UNITS
V
mA
mA
V
mV
mV
mV
mV
mV
mV
mV
μV/°C
μA
μA
dB
dB
V
V
CC
= 5V
V
CC
= 3V
(Note 2)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
–0.1
–2.0
–3.0
–5.5
–6.5
1.0
2.0
–6
55
65
V
CC
– 0.4
70
80
∞
3.5
10
3.0
4.5
7.0
0
0.6
0.4
4.5
7
6.5
8.0
10
13
V
ns
ns
ns
ns
17201fc
3
LT1720/LT1721
ELECTRICAL CHARACTERISTICS
SYMBOL
Δt
PD
t
SKEW
t
r
t
f
t
JITTER
f
MAX
PARAMETER
Differential Propagation Delay
Propagation Delay Skew
Output Rise Time
Output Fall Time
Output Timing Jitter
Maximum Toggle Frequency
The
l
denotes specifications that apply over the full operating temperature
,
range, otherwise specifications are at T
A
= 25°C. V
CC
= 5V, V
CM
= 1V, C
OUT
= 10pF V
OVERDRIVE
= 20mV, unless otherwise specified.
CONDITIONS
(Note 9) Between Channels
(Note 10) Between t
PDLH
/t
PDHL
10% to 90%
90% to 10%
V
IN
= 1.2V
P-P
(6dBm), Z
IN
= 50Ω
V
CM
= 2V, f = 20MHz
V
OVERDRIVE
= 50mV, V
CC
= 3V
V
OVERDRIVE
= 50mV, V
CC
= 5V
t
PDLH
t
PDHL
MIN
TYP
0.3
0.5
2.5
2.2
15
11
70.0
62.5
MAX
1.0
1.5
UNITS
ns
ns
ns
ns
ps
RMS
ps
RMS
MHz
MHz
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
If one input is within these common mode limits, the other input
can go outside the common mode limits and the output will be valid.
Note 3:
The LT1720/LT1721 comparators include internal hysteresis.
The trip points are the input voltage needed to change the output state in
each direction. The offset voltage is defined as the average of V
TRIP+
and
V
TRIP–
, while the hysteresis voltage is the difference of these two.
Note 4:
The common mode rejection ratio is measured with V
CC
= 5V
and is defined as the change in offset voltage measured from V
CM
= –0.1V
to V
CM
= 3.8V, divided by 3.9V.
Note 5:
The power supply rejection ratio is measured with V
CM
= 1V and
is defined as the change in offset voltage measured from V
CC
= 2.7V to
V
CC
= 6V, divided by 3.3V.
Note 6:
Because of internal hysteresis, there is no small-signal region
in which to measure gain. Proper operation of internal circuity is ensured
by measuring V
OH
and V
OL
with only 10mV of overdrive.
Note 7:
Propagation delay measurements made with 100mV steps.
Overdrive is measured relative to V
TRIP
±
.
Note 8:
t
PD
cannot be measured in automatic handling equipment with
low values of overdrive. The LT1720/LT1721 are 100% tested with a
100mV step and 20mV overdrive. Correlation tests have shown that
t
PD
limits can be guaranteed with this test, if additional DC tests are
performed to guarantee that all internal bias conditions are correct.
Note 9:
Differential propagation delay is defined as the larger of the two:
Δt
PDLH
= t
PDLH(MAX)
– t
PDLH(MIN)
Δt
PDHL
= t
PDHL(MAX)
– t
PDHL(MIN)
where (MAX) and (MIN) denote the maximum and minimum values
of a given measurement across the different comparator channels.
FPGA/CPLD
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