ASAHI KASEI
[AKD4117-B]
AKD4117-B
AK4117 Evaluation Board Rev.0
GENERAL DESCRIPTION
AKD4117-B is the evaluation board for AK4117, 192kHz digital audio receiver. This board has optical
connector and BNC connector to interface with other digital audio equipment.
Ordering guide
AKD4117-B ---
Evaluation board for AK4117
(A cable for connecting with printer port of IBM-AT compatible PC
and a control software are packed with this. The control software
does not operate on Windows NT.)
FUNCTION
Digital interface
-S/PDIF :
8 channel input (optical or BNC)
- Serial audio data I/F :
1 output (for DIR data output. 10-pin port)
-U bit :
-Serial control data I/F
1 input/output port (10-pin port)
5V
REG
3.3V
GND
Control
Opt
RX0
AK4117
RX1
Serial Data out
(From DIR)
Figure 1. AKD4117-B Block Diagram
*Circuit diagram and PCB layout are attached at the end of this manual.
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ASAHI KASEI
[AKD4117-B]
Evaluation Board Manual
Operating sequence
(1)
Set up the power supply lines.
[+ 5V]
(Red) = 5V
[GND]
(Black) = 0V
(2)
Set up the evaluation mode and jumper pins.
(Refer to the following item.)
(3)
Connect cables.
(Refer to the following item.)
(4)
Power on.
The AK4117 should be reset once bringing PDN(SW2) “L” upon power-up.
Evaluation modes
(1) Evaluation for DIR
MCLK
BICK
LRCK
SDTO
S/PDIF
Optical or BNC
connector
AK4117
(DIR)
PORT2
(10pin Header)
MCLK
BICK
LRCK
SDTO
DAC
AKD4117-B
The DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical
connector(PORT1: TORX176) or BNC connector . The AKD4117-B can be connected with the AKM’s DAC
evaluation board via 10-line cable.
a.
Set-up of Bi-phase Input
RX0 and RX1 should not select BNC at the same time.
a-1. RX0
Connector
JP2(RX0)
Optical (PORT1)
OPT
BNC (J2)
BNC
Table 1. Set-up of RX0
When S/PDIF signal is inputted from PORT1 (optical), JP19 should be short.
a-2. RX1 can be inputted from a BNC (J2) connector only.
RX1
JP4
JP
Short
Table 2. Set-up of RX1
Input
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ASAHI KASEI
[AKD4117-B]
a-3. Set-up of AK4117 input path
IPS bit
0
1
Input data
RX0
RX1
Default
Table 3. Recovery Data Select
b.
Set-up of clock input and output
The signal level outputted/inputted from PORT2 is 3.3V.
DAUX
NC
MCLK
SDTO
LRCK
BICK
PORT2
DIR
1
5
GND
GND
GND
10
Figure 2. PORT2 pin layout
b-1. MCKO1/MCKO2
The AK4117 has a master clock output pin, MCKO. In PLL mode, PCKS1-0 bits select the MCKO frequency as
shown in
Table 4
. When MCKO=512fs, MCKO goes to “L” when fs=96kHz and 192kHz. When MCKO=256fs,
MCKO goes to “L” when fs=192kHz. When LP bit is set to “1”, the AK4117 is in low power mode (default). In
low power mode, PLL lock range is up to 48kHz and the MCKO frequency is fixed to 256fs.
In the X’tal mode, XCKS1-0 bits select the ratio of the X’tal frequency to fs (sampling frequency). The DIV bit
selects the ratio (x1 or x1/2) of the MCKO frequency to the X’tal frequency (
Table 5
).
LP
0
PCKS1
0
0
1
1
x
PCKS0
0
1
0
1
x
MCKO
512fs
256fs
128fs
N/A
256fs
fs [kHz]
32
∼
48
32
∼
96
32
∼
192
N/A
32
∼
48
GND
6
1
Default
Table 4. Master Clock Frequency Select
(PLL mode: Clock operation mode 0, 2(UNLCK=0))
XCKS1
0
0
1
1
XCKS0
0
1
0
1
X’tal
or
EXT
128fs
256fs
512fs
1024fs
MCKO
DIV=0
128fs
256fs
512fs
1024fs
DIV=1
64fs
128fs
256fs
512fs
fs [kHz]
EXTCLK [MHz]
2.048
4.096
8.192
16
32
64
8
16
32
N/A
8
16
N/A
N/A
8
X’tal [MHz]
11.2896 12.288
24.576
88.2
96
192
44.1
48
96
N/A
N/A
48
N/A
N/A
N/A
Default
Table 5. Master Clock Frequency Select
(X’tal mode: Clock operation mode 1, 2(UNLCK=1), 3)
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ASAHI KASEI
[AKD4117-B]
c.
Set-up of Audio format
Please set up DIF2-0 bit.
Mode
0
1
2
3
4
5
6
7
DIF2
bit
0
0
0
0
1
1
1
1
DIF1
bit
0
0
1
1
0
0
1
1
DIF0
bit
0
1
0
1
0
1
0
1
DAUX
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I
2
S
SDTO
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I
2
S
Reserved
Table 6. Audio format
LRCK
I/O
H/L
O
H/L
O
H/L
O
H/L
O
H/L
O
L/H
O
Default
d.
Set-up of CM1 and CM0
The operation mode of PLL is selected by CM1 and CM0. It can be selected by CM1-0 bits.
CM1 bit
0
0
1
1
CM0 bit
0
1
0
1
(UNLOCK)
-
-
0
1
-
PLL
ON
OFF
ON
ON
ON
X'tal
ON(Note 1)
ON
ON
ON
ON
Clock source
PLL(RX)
X'tal
PLL(RX)
X'tal
X'tal
SDTO
source
RX
DAUX
RX
DAUX
DAUX
Default
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF.
Table 7. Clock Operation Mode Select
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ASAHI KASEI
[AKD4117-B]
U output
U(user data) can be monitored by TP1: U.
Serial control
The AK4117 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT6
(uP-I/F) with PC by 10-line flat cable packed with the AKD4117-B. Take care of the direction of connector. There
is a mark at pin#1. The pin layout of PORT6 is as
Figure 3
.
PORT6
uP I/F
2
GND
GND
GND
GND
GND
10
1
Figure 3. PORT6 pin layout
This evaluation board encloses control software. A software operation procedure is included in an evaluation board
manual.
<KM077200>
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CDTO
CCLK
CSN
NC
CDTI
9
2004/12
嵌入式系统
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