Datasheet
RX130 Group
Renesas MCUs
R01DS0273EJ0300
Rev.3.00
Aug 09, 2018
32-MHz, 32-bit RX MCUs, 50 DMIPS, up to 512-KB flash memory,
up to 36 pins capacitive touch sensing unit, up to 6 comms channels, 12-bit A/D, D/A, RTC,
IEC60730 compliance, 1.8-V to 5.5-V single supply
Features
■ 32-bit RX CPU core
•
Max. operating frequency: 32 MHz
Capable of 50 DMIPS in operation at 32 MHz
•
Accumulator handles 64-bit results (for a single instruction) from
32-bit × 32-bit operations
•
Multiplication and division unit handles 32-bit × 32-bit operations
(multiplication instructions take one CPU clock cycle)
•
Fast interrupt
•
CISC Harvard architecture with 5-stage pipeline
•
Variable-length instructions, ultra-compact code
•
On-chip debugging circuit
PLQP0100KB-B
PLQP0080KB-B
PLQP0064GA-A
PLQP0064KB-C
PLQP0048KB-B
14 × 14mm, 0.5mm pitch
12 × 12mm, 0.5mm pitch
14 × 14mm, 0.8mm pitch
10 × 10mm, 0.5mm pitch
7 × 7mm, 0.5mm pitch
■ Low power design and architecture
•
•
•
•
Operation from a single 1.8-V to 5.5-V supply
Three low power consumption modes
Low power timer (LPT) that operates during the software standby state
Supply current
High-speed operating mode: 96 µA/MHz
Supply current in software standby mode: 0.37 µA
•
Recovery time from software standby mode: 4.8 µs
PWQN0048KB-A 7 × 7mm, 0.5mm pitch
■ MPC
•
Input/output functions selectable from multiple pins
■ On-chip flash memory for code, no wait states
•
•
•
•
•
64 K/128 K/256 K/383 K/512 Kbytes
Operation at 32 MHz, read cycle of 31.25 ns
No wait states for reading at full CPU speed
Programmable at 1.8 V
For instructions and operands
■ Up to 6 communication functions
■ On-chip data flash memory
•
8 Kbytes (1,000,000 program/erase cycles (typ.))
•
BGO (Background Operation)
•
SCI with many useful functions (up to 4 channels)
Asynchronous mode (Fine adjustable baud rate: 0 to 255/255), clock
synchronous mode, smart card interface mode
•
I
2
C bus interface: Transfer at up to 400 kbps, capable of SMBus
operation (one channel)
•
RSPI (one channel): Transfer at up to 16 Mbps
•
Two units integrated
•
Four pattern waveform matching supported
•
16-bit MTU: input capture, output compare, complementary PWM
output, phase counting mode (six channels)
•
8-bit TMR (four channels)
•
16-bit compare-match timers (two channels)
•
•
•
•
•
Capable of conversion within 1.4 μs
17 channels
Sampling time can be set for each channel
Conversion results compare features
Self-diagnostic function and analog input disconnection detection
assistance function
•
Double trigger (data duplication) function for motor control
■ Remote control signal reception
■ On-chip SRAM, no wait states
■ DTC
•
10 K/16 K/32 K/48 Kbytes size capacities
•
Four transfer modes
•
Transfer can be set for each interrupt source.
■ Up to 12 extended-function timersMPC
■ ELC
■ 12-bit A/D converter
•
Module operation can be initiated by event signals without using
interrupts.
•
Linked operation between modules is possible while the CPU is sleeping.
•
Eight types of reset, including the power-on reset (POR)
•
Low voltage detection (LVD) with voltage settings
•
•
•
•
•
•
•
•
•
External clock input frequency: Up to 20 MHz
Main clock oscillator frequency: 1 to 20 MHz
Sub clock oscillator frequency: 32.768 kHz
PLL circuit input: 4 MHz to 8 MHz
Low-speed on-chip oscillator: 4 MHz
High-speed on-chip oscillator: 32 MHz ± 1 %
IWDT-dedicated on-chip oscillator: 15 kHz
Generate a 32.768 kHz clock for the real-time clock
On-chip clock frequency accuracy measurement circuit (CAC)
■ Reset and supply management
■
Clock functions
■ D/A converter
•
Two channels
■ Capacitive touch sensing unit
•
Self-capacitance method: A single pin configures a single key,
supporting up to 36 keys
•
Mutual capacitance method: Matrix configuration with 36pins, supporting
up to 324 keys
■ Comparator B
•
Two channels
■ Realtime clock
■ General I/O ports
•
Adjustment functions (30 seconds, leap year, and error)
•
Calendar count mode or binary count mode selectable
•
15-kHz on-chip oscillator produces a dedicated clock signal to drive
IWDT operation.
•
Self-diagnostic and disconnection-detection assistance functions for
the A/D converter, clock frequency accuracy measurement circuit,
independent watchdog timer, RAM test assistance functions using the
DOC, etc.
•
5-V tolerant, open drain, input pull-up, switching of driving capacity
■ Independent watchdog timer
■ Temperature sensor
■ Unique ID
•
–40 to +85°C
•
–40 to +105°C
•
32-byte ID code for the MCU
■ Useful functions for IEC60730 compliance
■ Operating temperature range
■ Applications
•
General industrial and consumer equipment
R01DS0273EJ0300 Rev.3.00
Aug 09, 2018
Page 1 of 134
RX130 Group
1. Overview
1.
1.1
Overview
Outline of Specifications
Table 1.1
lists the specifications, and
Table 1.2
gives a comparison of the functions of the products in different
packages.
Table 1.1
is for products with the greatest number of functions, so the number of peripheral modules and channels will
differ in accordance with the package type. For details, see
Table 1.2, Comparison of Functions for Different
Packages in the RX130 Group.
Table 1.1
Classification
CPU
Outline of Specifications (1/3)
Module/Function
CPU
Description
•
•
•
•
•
Maximum operating frequency: 32 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per clock cycle
Address space: 4-Gbyte linear
Register set
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit registers
Basic instructions: 73 (variable-length instruction format)
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit
On-chip divider: 32-bit ÷ 32-bit → 32 bits
Barrel shifter: 32 bits
•
•
•
•
•
•
•
Memory
ROM
•
Capacity: 64 K/128 K/256 K/383 K/512 Kbytes
•
No-wait memory access
•
Programming/erasing method:
Serial programming (asynchronous serial communication), self-programming
•
Capacity: 10 K/16 K/32 K/48 Kbytes
•
No-wait memory access
•
Capacity: 8 Kbytes
•
Number of erase/write cycles: 1,000,000 (typ)
Single-chip mode
•
Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator
•
Oscillation stop detection: Available
•
Clock frequency accuracy measurement circuit (CAC)
•
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization with the PCLKB: 32 MHz (at max.)
The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)
•
The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1,2,4,8,16,32,64)
RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
RAM
E2 DataFlash
MCU operating mode
Clock
Clock generation circuit
Resets
Voltage detection
Voltage detection circuit
(LVDAb)
•
When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 14 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
•
Module stop function
•
Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
•
Operating power control modes
High-speed operating mode, middle-speed operating mode, and low-speed operating mode
•
Interrupt vectors: 115
•
External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
•
Non-maskable interrupts: 5 (The NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, and IWDT interrupt)
•
16 levels specifiable for the order of priority
Low power
consumption
Low power consumption
functions
Function for lower operating
power consumption
Interrupt
Interrupt controller (ICUb)
R01DS0273EJ0300 Rev.3.00
Aug 09, 2018
Page 2 of 134
RX130 Group
Table 1.1
Classification
DMA
1. Overview
Outline of Specifications (2/3)
Module/Function
Data transfer controller
(DTCa)
General I/O ports
Description
•
Transfer modes: Normal transfer, repeat transfer, and block transfer
•
Activation sources: Interrupts
•
Chain transfer function
100-pin /80-pin /64-pin /48-pin
•
I/O: 88/68/52/38
•
Input: 1/1/1/1
•
Pull-up resistors: 88/68/52/38
•
Open-drain outputs: 67/47/35/26
•
5-V tolerance: 4/4/2/2
•
Event signals of 47 types can be directly connected to the module
•
Operations of timer modules are selectable at event input
•
Capable of event link operation for port B
Capable of selecting the input/output function from multiple pins
•
(16 bits × 6 channels) × 1 unit
•
Up to 16 pulse-input/output lines and three pulse-input lines are available based on the six 16-bit
timer channels
•
Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
•
Input capture function
•
21 output compare/input capture registers
•
Pulse output mode
•
Complementary PWM output mode
•
Reset synchronous PWM mode
•
Phase-counting mode
•
Capable of generating conversion start triggers for the A/D converter
Controls the high-impedance state of the MTU’s waveform output pins
•
(16 bits × 2 channels) × 1 unit
•
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
•
14 bits × 1 channel
•
Count clock: Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
•
Clock source: Sub-clock
•
Calendar count mode or binary count mode selectable
•
Interrupts: Alarm interrupt, periodic interrupt, and carry interrupt
•
16 bits × 1 channel
•
Clock source: Sub-clock, Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 2, 4, 8, 16, or 32
•
(8 bits × 2 channels) × 2 units
•
Seven internal clocks (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, and PCLK/8192)
and an external clock can be selected
•
Pulse output and PWM output with any duty cycle are available
•
Two channels can be cascaded and used as a 16-bit timer
•
7 channels (channel 0, 1, 5, 6, 8, 9: SCIg, channel 12: SCIh)
•
SCIg
Serial communications modes: Asynchronous, clock synchronous, and smart-card interface
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12
Start-bit detection: Level or edge detection is selectable.
Simple I
2
C
Simple SPI
9-bit transfer mode
Bit rate modulation
Event linking by the ELC (only on channel 5)
•
SCIh (The following functions are added to SCIg)
Supports the serial communications protocol, which contains the start frame and information frame
Supports the LIN format
•
•
•
•
1 channel
Communications formats: I
2
C bus format/SMBus format
Master mode or slave mode selectable
Supports fast mode
I/O ports
Event link controller (ELC)
Multi-function pin controller (MPC)
Timers
Multi-function timer pulse
unit 2 (MTU2a)
Port output enable 2
(POE2a)
Compare match timer
(CMT)
Independent watchdog
timer (IWDTa)
Realtime clock (RTCc)*
1
Low power timer (LPT)
8-bit timer (TMR)
Communication
functions
Serial communications
interfaces (SCIg, SCIh)
I
2
C bus interface (RIICa)
R01DS0273EJ0300 Rev.3.00
Aug 09, 2018
Page 3 of 134
RX130 Group
Table 1.1
Classification
Communication
functions
1. Overview
Outline of Specifications (3/3)
Module/Function
Serial peripheral interface
(RSPIa)
Description
•
1 channel
•
Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPCK
(RSPI clock) signals enables serial transfer through SPI operation (four lines) or
clock-synchronous operation (three lines)
•
Capable of handling serial transfer as a master or slave
•
Data formats
•
Choice of LSB-first or MSB-first transfer
The number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or
32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each frame
having up to 32 bits)
•
Double buffers for both transmission and reception
•
•
•
•
•
•
•
•
2 channels
Four pattern matching (header, data 0, data 1, and special data detection)
8-byte receive buffer per unit
The operating clock can be selected from among the PCLK, sub-clock, HOCO, IWDTCLK, and TMR.
12 bits (24 channels × 1 unit)
12-bit resolution
Minimum conversion time: 1.4 µs per channel when the ADCLK is operating at 32 MHz
Operating modes
Scan mode (single scan mode, continuous scan mode, and group scan mode)
Group A priority control (only for group scan mode)
Sampling variable
Sampling time can be set up for each channel.
Self-diagnostic function
Double trigger mode (A/D conversion data duplicated)
Detection of analog input disconnection
Conversion results compare features
A/D conversion start conditions
A software trigger, a trigger from a timer (MTU), an external trigger signal, or ELC
Event linking by the ELC
Remote control signal
receiver (REMC)
12-bit A/D converter (S12ADE)
•
•
•
•
•
•
•
Temperature sensor (TEMPSA)
•
1 channel
•
The voltage output from the temperature sensor is converted into a digital value by the 12-bit A/D
converter.
•
2 channels
•
8-bit resolution
•
Output voltage: 0V to AVCC0
•
CRC code generation for arbitrary amounts of data in 8-bit units
•
Select any of three generating polynomials:
X
8
+ X
2
+ X + 1, X
16
+ X
15
+ X
2
+ 1, or X
16
+ X
12
+ X
5
+ 1
•
Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.
•
2 channels
•
Function to compare the reference voltage and the analog input voltage
•
Window comparator operation or standard comparator operation is selectable
Detection pin: 36 channels
Comparison, addition, and subtraction of 16-bit data
32-byte ID code for the MCU
VCC = 1.8 to 2.4 V: 8 MHz, VCC = 2.4 to 2.7 V: 16 MHz, VCC = 2.7 to 5.5 V: 32 MHz
D version: –40 to +85°C, G version: –40 to +105°C
100-pin LFQFP (PLQP0100KB-B) 14 × 14 mm, 0.5 mm pitch
80-pin LFQFP (PLQP0080KB-B) 12 × 12 mm, 0.5 mm pitch
64-pin LFQFP (PLQP0064KB-C) 10 × 10 mm, 0.5 mm pitch
64-pin LQFP (PLQP0064GA-A) 14 × 14 mm, 0.8 mm pitch
48-pin LFQFP (PLQP0048KB-B) 7 × 7 mm, 0.5 mm pitch
48-pin HWQFN (PWQN0048KB-A) 7 × 7 mm, 0.5 mm pitch
FINE interface
D/A converter (DA)
CRC calculator (CRC)
Comparator B (CMPBa)
Capacitive touch sensing unit (CTSUa)
Data operation circuit (DOC)
Unique ID
Power supply voltages/Operating frequencies
Operating temperature range
Packages
Debugging interfaces
Note 1. When the realtime clock is not to be used, refer to section 24.5.7, Initialization Procedure When the Realtime Clock is Not to be
Used.
R01DS0273EJ0300 Rev.3.00
Aug 09, 2018
Page 4 of 134
RX130 Group
Table 1.2
Comparison of Functions for Different Packages in the RX130 Group
RX130 Group
Module/Functions
Interrupts
External interrupts
100 Pins
80 Pins
NMI,
IRQ0 to IRQ7
Available
6 channels (MTU0 to MTU5)
POE0# to POE3#, POE8#
2 channels × 2 units
2 channels × 1 unit
1 channel
Available
Available
6 channels
(SCI0, 1, 5, 6, 8, 9)
3 channels (SCI1, 5, 6)
1 channel (SCI12)
1 channel
1 channel
2 channels
36 channels
24 channels
36 channels
17 channels
Available
2 channels
Available
Available
2 channels
100-pin LFQFP
(0.5 mm)
80-pin LFQFP
(0.5 mm)
64-pin LQFP
(0.8 mm)
64-pin LFQFP
(0.5 mm)
Not supported
32 channels
14 channels
64 Pins
NMI,
IRQ0 to IRQ2,
IRQ4 to IRQ7
48 Pins
1. Overview
NMI,
IRQ0, IRQ1,
IRQ4 to IRQ7
DMA
Timers
Data transfer controller
Multi-function timer pulse
unit 2
Port output enable 2
8-bit timer
Compare match timer
Low power timer
Realtime clock
Independent watchdog
timer
Not supported
Communication
functions
Serial communications
interfaces (SCIg)
Serial communications
interfaces (SCIh)
I
2
C bus interface
Serial peripheral interface
Remote control signal
receiver (REMC)
Capacitive touch sensing unit
12-bit A/D converter
Temperature sensor
D/A converter
CRC calculator
Event link controller
Comparator B
Packages
24 channels
10 channels
Not supported
48-pin LFQFP
(0.5 mm)
48-pin HWQFN
(0.5 mm)
R01DS0273EJ0300 Rev.3.00
Aug 09, 2018
Page 5 of 134
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