ASAHI KASEI
[AK6510C/12C]
AK6510C / 12C
SPI bus 32K/64Kbit Serial CMOS EEPROM
Features
Advanced CMOS EEPROM Technology
Single Voltage Supply: 1.8V to 5.5V
AK6510C: 32Kbits; 4096 x 8 organization
AK6512C: 64Kbits; 8192 x 8 organization
SPI Serial Interface Compatible
Low Power Consumption
0.8µA Max. (Standby mode)
High Reliability
Endurance:
1000K E/W cycles / Address
Data Retention: 10 Years
Special Features
32 byte Page Write Mode
Block Write Protection (Protect 1/4,1/2 or Entire Array)
Automatic write cycle time-out with auto-ERASE
Software and Hardware controlled Write Protection
Self timed Programming Cycle: 5msec. Max.
Ideal for Low Density Data Storage
Low cost, space saving, 8-pin SSOP/SONW package
SO
DATA
REGISTER
SI
INSTRUCTION
REGISTER
R/W AMPS
AND
AUTO ERASE
INSTRUCTION
DECODE,
CONTROL
AND
CLOCK
GENERATION
EEPROM
AK6510C=32Kbit
AK6512C=64Kbit
ADD.
BUFFERS
DECODER
CS
VPP SW
SCK
HOLD
WP
VREF
VPP
GENERATOR
STATUS REGISTER
Block Diagram
DAP02E-04
- 1 -
2005/03
ASAHI KASEI
[AK6510C/12C]
General Description
The AK6510C/12C is a 32768/65536-bit, serial, read/write, non-volatile memory device fabricated
using an advanced CMOS EEPROM technology. The AK6510C/12C has 32768-bits/65536-bits of
memory organized as 4096/8192 registers of 8 bits each. The AK6510C/12C can operate all
function under wide operating voltage range: 1.8V to 5.5V. The charge up circuit for high voltage
generation needed for write operations is integrated.
The AK6510C/12C serial interface is compatible to a SPI bus. The AK6510C/12C has 6
instructions: READ, WRITE, WREN (write enable), WRDI (write disable), RDSR (read status
register), and WRSR (write status register).
Each instruction is organized by an op-code (8bits), address (16bits), and data (8bits). When input
level of CS pin changed from high level to low level, AK6510C/12C can receive instructions.
Pin Configurations
AK6510CM/12CM
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
WP
GND
AK6510CL/12CL
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8pin SSOP
8pin SONW
Pin name
CS
SCK
SI
SO
WP
HOLD
VCC
GND
Functions
Chip Select input
Serial Clock input
Serial Data input
Serial Data output
Write Protect input
Hold input
Power Supply
Ground
Type of Products
Model
AK6510CM
AK6510CL
AK6512CM
AK6512CL
Memory size
32K bits
64K bits
Temp. Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VCC
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
Package
8pin Plastic SSOP
8pin Plastic SONW
8pin Plastic SSOP
8pin Plastic SONW
DAP02E-04
- 2 -
2005/03
ASAHI KASEI
[AK6510C/12C]
Data Transfer
An IC that outputs the clock is called "MASTER", an IC that receives the clock is called "SLAVE".
The AK6510C/12C operates as a SLAVE. Data is written to the SI pin and read from SO pin. The
MSB is transmitted first.
After CS pin changes hi level to low level, AK6510C/12C receives the first data bit on the SI pin
synchronously with the rising edge of the input pulse of serial clock. While CS pin is high level, the
data input to the SI pin is don’t care and SO pin indicates Hi-Z.
All the functions are organized 8 bits of op-code, address, and data. If there is an invalid op-code,
the AK6510C/12C ignores the address and data information and SO pin indicates Hi-Z. In order to
input new op-code, CS pin should be toggled.
Hold
AK6510C/12C has a HOLD pin that can hold the data transfer. When HOLD changes high to low
while SCK is low, the data transfer stops. After the HOLD pin changes low to High while SCK is
low, the data transfer starts again. While the data transfer is paused, AK6510C/12C ignores the
clock on the SCK line.
Write Protect
AK6510C/12C has status registers. When the WPEN bit in the status registers is "1", Write Protect
function is enabled. When WPEN bit is "1" and WP pin is low level, the status register is protected
from write function. When WP pin becomes low level while the WRITE to the status register
instruction is written, the AK6510C/12C doesn’t accept the instruction. When the WP pin changes
low level while the internal programming, the programming function continues.
When the WPEN bit is "0", WP pin function is disabled. Even if WP pin is fixed to low level, the
WRITE function to the status register can be done. When the WP pin is high level, AK6510C/12C
can accept all of READ and WRITE functions.
DAP02E-04
- 3 -
2005/03
ASAHI KASEI
[AK6510C/12C]
Pin Description
CS
(Chip Select Input)
When CS changes high level to low level, the AK6510C/12C can receive the instructions.
CS should be kept low level while receiving op-code, address and data, and while outputting
data.
When CS is high level, SO indicate Hi-Z.
SCK
(Serial Clock Input)
The SCK clock pin is the synchronous clock input for input/output data.
SI
(Serial Data Input)
The op-code, address, and data are written to the SI pin.
SO
(Serial Data Output)
The SO pin outputs the data from memory array and status register.
WP
(Write Protect Input)
The WP pin controls the write function to the status register.
When the WPEN bit in the status register is "0", the function of WP pin becomes disable.
Then the status register can be programmable when the WEN bit in the status register is "1".
And it does not depend on the status of WP pin.
When the WPEN bit is "1", the function of WP is enabled. Then the status register can not
be programmable when the WEN bit is "1" and the status of WP pin is low.
When the WPEN bit is "1", WP pin is high and WEN bit is "1", AK6510C/12C can accept the
WRITE instruction to the status registers.
During the instruction input, WP pin should keep high or low level.
HOLD
(Hold Input)
The HOLD pin can hold the data transfer. When the HOLD pin changes hi to low while the
SCK is low, the data transfer is held. And the transfer starts when the HOLD pin changes
low to high while the SCK is low. While the holding the data transfer, AK6510C/12C ignores
the clock signal on SCK pin.
DAP02E-04
- 4 -
2005/03
ASAHI KASEI
[AK6510C/12C]
Function Description
AK6510C/12C has six instructions. The instruction can be input after the CS pin changes high to
low. All the instructions are MSB first.
Instruction
READ
WRITE
WREN
WRDI
RDSR
WRSR
Op-code
0000 X011
0000 X010
0000 X110
0000 X100
0000 X101
0000 X001
Address
X X X A12-A8
X X X A12-A8
------
------
Bit7-Bit0 (out)
Bit7-Bit0 (in)
------
------
A7-A0
A7-A0
Data
D7-D0 (out)
D7-D0 (in)
------
------
------
------
Description
Read from Memory Array
Write to Memory Array
Write Enable
Write Disable
Read Status Register
Write Status Register
X: don’t care
AK6510C: A12 is don’t care
Table 1. Instruction set for AK6510C/12C
WREN (WRITE ENABLE) / WRDI (WRITE DISABLE)
The WRITE function can be accepted only in the status of Write Enable. After VCC is applied,
AK6510C/12C is in the status of Write Disable. After the function of WRDI, AK6510C/12C cannot
accept any programming function.
CS
SCK
SI
SO
0
1
2
3
4
5
6
7
0
0
0
0
X
Hi-Z
1
1
0
X = don’t care
WREN
CS
SCK
SI
SO
0
1
2
3
4
5
6
7
0
0
0
0
X
Hi-Z
1
0
0
X = don’t care
WRDI
DAP02E-04
- 5 -
2005/03
FPGA/CPLD
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