NJM2073
DUAL LOW VOLTAGE POWER AMPLIFIER
■
GENERAL DESCRIPTION
The NJM2073 is a monolithic integrated circuit in 8 lead
dual-in-line package,which is designed for dual audio power
amplifier in portable radio and handy cassette player.
■
FEATURES
●
Operating Voltage
●
Low Crossover Distortion
●
Low Operating Current
●
Bridge or Stereo Configuration
●
No Turn-on Noise
●
Package Outline
●
Bipolar Technology
■
PIN CONFIGURATION
■
PACKAGE OUTLINE
( V
+
=1.8V~15V )
NJM2073D
NJM2073M
DIP8,DMP8
NJM2073D
NJM2073M
Ver.2004-03-01
-1-
NJM2073
■
ABSOLUTE MAXIMUM RATINGS
( Ta=25˚C )
PARAMETER
Supply Voltage
Output Peak Current
Power Dissipation
Input Voltage Range
Operating Temperature Range
Storage Temperature Range
SYMBOL
V
I
OP
P
D
V
IN
T
opr
T
stg
+
RATINGS
15
1
( DIP8 ) 700
( DMP8 ) 300
± 0.4
-40~+85
-40~+125
UNIT
V
A
mW
V
˚C
˚C
■
ELECTRICAL CHARACTERISTICS D-Type
(1) BTL Configuration ( Test Circuit Fig.1 )
PARAMETER
Operating Voltage
Operating Current
Output Offset Voltage
( Between the Outputs )
Input Bias Current
Output Power
SYMBOL
V
+
I
CC
∆V
O
I
B
P
O
P
O
P
O
P
O
P
O
P
O
P
O
P
O
THD
A
V
Z
IN
V
NI1
V
NI2
RR
f
H
THD=10%,f=1kHz
V
+
=9V,R
L
=16Ω ( Note )
V
+
=6V,R
L
=8Ω ( Note )
V
+
=4.5V,R
L
=8Ω
V
+
=4.5V,R
L
=4Ω ( Note )
V
+
=3V,R
L
=4Ω
V
+
=2V,R
L
=4Ω
THD=1%,f=40Hz~15kHz
V
+
=6V,R
L
=8Ω
V
+
=4.5V,R
L
=4Ω
P
O
=0.5W,R
L
=8Ω,f=1kHz
f=1kHz
f=1kHz
R
S
=10kΩ,A Curve
R
S
=10kΩ,B=22Hz~22kHz
f=100Hz
A
V
=-3dB from f=1kHz,R
L
=8Ω,P
O
=1W
TEST CONDITION
R
L
=∞
R
L
=8Ω
MIN.
1.8
-
-
-
-
0.9
-
-
200
-
-
-
-
41
100
-
-
-
-
TYP.
-
6
10
100
2.0
1.2
0.6
0.8
300
80
1.0
0.6
0.2
44
-
2
2.5
40
130
( V
+
=6V,Ta=25˚C )
MAX.
15
9
50
-
-
-
-
-
-
-
-
-
-
47
-
-
-
-
-
UNIT
V
mA
mV
nA
W
W
W
W
mW
mW
W
W
%
dB
kΩ
µV
µV
dB
kHz
Total Harmonic Distortion
Close Loop Voltage Gain
Input Impedance
Equivalent Input Noise Voltage
Ripple Rejection
Cutoff Frequency
( Note ) At on PC Board
-2-
Ver.2004-03-01
NJM2073
(2) Stereo Configuration ( Test Circuit Fig.2 )
PARAMETER
Operating Voltage
Output Voltage
Operating Current
Input Bias Current
Output Power ( Each Channel )
SYMBOL
+
V
V
O
I
CC
I
B
P
O
P
O
P
O
P
O
P
O
P
O
THD
A
V
∆A
V
Z
IN
V
NI1
V
NI2
RR
f
H
TEST CONDITION
R
L
=∞
THD=10%,f=1kHz
V
+
=6V,R
L
=4Ω ( Note )
V
+
=4.5V,R
L
=4Ω
V
+
=3V,R
L
=4Ω
V
+
=2V,R
L
=4Ω
THD=1%,f=1kHz
V
+
=6V,R
L
=4Ω
V
+
=4.5V,R
L
=4Ω
P
O
=0.4W,R
L
=4Ω,f=1kHz
f=1kHz
f=1kHz
R
S
=10kΩ,A Curve
R
S
=10kΩ,B=22Hz~22kHz
f=100Hz,C
X
=100µF
A
V
=-3dB from f=1kHz,R
L
=8Ω,P
O
=250mW
MIN.
1.8
-
-
-
0.5
-
-
-
-
-
-
41
-
100
-
-
24
-
TYP.
-
2.7
6
100
0.65
0.32
120
30
500
250
0.25
44
-
-
2.5
3
30
200
MAX.
15
-
9
-
-
-
-
-
-
-
-
47
±1
-
-
-
-
-
UNIT
V
V
mA
nA
W
W
mW
mW
mW
mW
%
dB
dB
kΩ
µV
µV
dB
kHz
Total Harmonic Distortion
Voltage Gain
Channel Balance
Input Impedance
Equivalent Input Noise Voltage
Ripple Rejection
Cutoff Frequency
( Note ) At on PC Board
■
ELECTRICAL CHARACTERISTICS M-Type
(1) BTL Configuration ( Test Circuit Fig.1 )
PARAMETER
Operating Voltage
Operating Current
Output Offset Voltage
( Between the Outputs )
Input Bias Current
Output Power
SYMBOL
V
+
I
CC
∆V
O
I
B
P
O
P
O
P
O
P
O
Total Harmonic Distortion
Close Loop Voltage Gain
Input Impedance
Equivalent Input Noise Voltage
Ripple Rejection
Cutoff Frequency
( Note ) At on PC Board
( V
+
=6V,Ta=25˚C )
TEST CONDITION
MIN.
1.8
-
-
-
TYP.
-
6
10
100
0.8
460
300
80
380
0.2
44
-
2
2.5
40
130
MAX.
15
9
50
-
-
-
-
-
-
-
47
-
-
-
-
-
UNIT
V
mA
mV
nA
W
mW
mW
mW
mW
%
dB
kΩ
µV
µV
dB
kHz
R
L
=∞
R
L
=8Ω
THD=10%,f=1kHz
V
+
=6V,R
L
=16Ω ( Note )
V
+
=4V,R
L
=8Ω ( Note )
V
+
=3V,R
L
=4Ω ( Note )
V
+
=2V,R
L
=4Ω
THD=1%,f=40Hz~15kHz
V
+
=4V,R
L
=8Ω
V
+
=4V,R
L
=8Ω,P
O
=200mW,f=1kHz
f=1kHz
f=1kHz
R
S
=10kΩ,A Curve
R
S
=10kΩ,B=22Hz~22kHz
f=100Hz
A
V
=-3dB from f=1kHz,R
L
=16Ω,P
O
=0.5W
-
350
200
-
-
-
41
100
-
-
-
-
P
O
THD
A
V
Z
IN
V
NI1
V
NI2
RR
f
H
Ver.2004-03-01
-3-
NJM2073
(2) Stereo Configuration ( Test Circuit Fig.2 )
PARAMETER
Operating Voltage
Output Voltage
Operating Current
Input Bias Current
Output Power ( Each Channel )
SYMBOL
+
V
V
O
I
CC
I
B
P
O
P
O
P
O
P
O
P
O
Total Harmonic Distortion
Voltage Gain
Channel Balance
Input Impedance
Equivalent Input Noise Voltage
Ripple Rejection
Cutoff Frequency
( Note ) At on PC Board
TEST CONDITION
R
L
=∞
THD=10%,f=1kHz
V
+
=6V,R
L
=16Ω
V
+
=5V,R
L
=8Ω ( Note )
V
+
=4V,R
L
=4Ω ( Note )
V
+
=3V,R
L
=4Ω
V
+
=2V,R
L
=4Ω
THD=1%,f=1kHz
V
+
=4V,R
L
=4Ω
V
+
=4V,R
L
=4Ω,P
O
=150mW,f=1kHz
f=1kHz
f=1kHz
R
S
=10kΩ,A Curve
R
S
=10kΩ,B=22Hz~22kHz
f=100Hz,C
X
=100µF
A
V
=-3dB from f=1kHz,R
L
=16Ω,P
O
=125mW
MIN.
1.8
-
-
-
-
-
180
-
-
-
-
41
-
100
-
-
24
-
TYP.
-
2.7
6
100
240
270
250
120
30
180
0.25
44
-
-
2.5
3
30
200
MAX.
15
-
9
-
-
-
-
-
-
-
-
47
±1
-
-
-
-
-
UNIT
V
V
mA
nA
mW
mW
mW
mW
mW
mW
%
dB
dB
kΩ
µV
µV
dB
kHz
P
O
THD
A
V
∆A
V
Z
IN
V
NI1
V
NI2
RR
f
H
■
TYPICAL APPLICATION & TEST CIRCUIT
Fig.1 BTL Configuration
Fig.2 Stereo Configuration
note:pin No.to D,M-Type
-4-
Ver.2004-03-01
NJM2073
■
PARASTIC OSCILLATION PREVEMTING CIRCUIT
Put 1Ω+0.22µF on parallel to load,if the load is speaker.Recommend putting 0.1µF and more than 100µF capacitors with good high
frequency characteristics in to near ground and supply voltage pins.
In BTL operation of less than 2V supply voltage,parastic oscillation may be occurred with R=1Ω.And so recommended R to be the
same value of pure resistance(r) when it is lower than 3V.
■
MUTING CIRCUIT
When Mute ON.OUTPUT level saturates to GND side.
Fig.3 BTL Configuration
Fig.4 Stereo Configuration
■
VOLTAGE GAIN REDUCTION APPLICATION EXAMPLE
(1) Outline of way to further Reduction
NJM2073 by taking in assamption,as one of OP-AMP ( Gain 44dB,minus input impedance about 300Ω ),to feedback from output to
minus input helps to get reduction of stabilized Voltage Gain.Fig.5 indicates the model example.
Here is the point to be noticed that,in order to get the appropriate output Bias Voltage,it is important to keep the minus input floating
as DC condition,(inserting C
X
),and also that when extended too much reduction of Gain might cause Oscillation due to high band
phase margin.The reduction of voltage gain is limited at around 26dB (20 times),and when oscillation,it in necessary to attach the
oscillation stopper.Please examine the C
X
value accordingly to the application requirement.
Fig.5 Model of Voltage Gain Reduction
Ver.2004-03-01
-5-
stm32/stm8
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