DEMO MANUAL DC1717A
LTC4417
Prioritized PowerPath™ Controller
Description
Demonstration circuit DC1717A uses the
LTC
®
4417
to
arbitrate between three input supply rails, selecting the
highest priority, valid supply to power the load. The rail’s
priority is defined by the input connection (V1-V3). Each
rail has overvoltage and undervoltage thresholds set by
external resistors. If the highest priority rail voltage falls
out of the defined window (overvoltage or undervoltage),
the rail with the next highest priority, which is valid, is
enabled and powers the load. Two or more LTC4417s
can be cascaded to provide switchover between more
than three rails.
Design files for this circuit board are available at
http://www.linear.com/demo/DC1717A
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
performance summary
SYMBOL
V1-V3, V
OUT
ΔV
G
ΔV
G(SOURCE)
ΔV
G(SINK)
ΔV
G(OFF)
ΔV
G(SLEW,ON)
ΔV
G(SLEW,OFF)
I
GATE(LOW)
V
REV
V
VALID(OL)
t
PVALID(OFF)
V
SHDN(THR)
V
SHDN_EN(HYS)
I
SHDN_EN
V
OV_UV(THR)
V
OV_UV(HYS)
t
VALID
V1
V2
V3
I
LOAD
AVI
PARAMETER
V1 to V3, V
OUT
Operating Supply Range
Open (VS-VG) Clamp Voltage
Sourcing (VS-VG) Clamp Voltage
Sinking (VS-VG) Clamp Voltage
G1 to G3 Off (VS-VG) Threshold
G1 to G3 Pull-Down Slew Rate
G1 to G3 Pull-Up Slew Rate
G1 to G3 Low Pull-Down Current
Reverse Voltage Threshold
VALID1
to
VALID3
Output Low Voltage
VALID1
to
VALID3
Delay OFF from
OV/UV Fault
SHDN
Threshold Voltage
SHDN,
EN Threshold Hysteresis
SHDN,
EN Pull-Up Current
OV1 to O3, UV1 to UV3 Comparator
Threshold
OV1 to O3, UV1 to UV3 Comparator
Hysteresis
V1 to V3 Validation Time
Operating Voltage of Channel V1
Operating Voltage of Channel V2
Operating voltage of Channel V3
Load Current
Auxiliary Voltage Input
Specifications are at T
A
= 25°C
CONDITIONS
V
OUT
= 11V, G1 to G3 = Open
V
OUT
= 11V, I = –10µA
V
OUT
= 11V, I = 10µA
V1 = V2 = V3 = 2.8V, V
OUT
= 2.6V, G1 to G3 Rising Edge
V
OUT
= 11V, C
GATE
= 10nF
V
OUT
= 11V, C
GATE
= 10nF
V
OUT
= 2.6V, V1 to V3 = 2.8V, (G1 to G3) = ΔV
G
+ 300mV
Measure (V1 to V3) – V
OUT
, V
OUT
Falling
V
OUT
= 11V, C
GATE
= 10nF
I = 1mA, (V1 to V3) = 2.5V, V
OUT
= 0V
5
SHDN
Rising
SHDN
= EN = 0V
V
OUT
= 11V, OV1 to OV3 Rising, UV1 to UV3 Falling
V
OUT
= 11V
0.4
–0.5
0.985
15
100
9.6
4
6.4
6
MIN
2.5
5.4
5.8
4.5
0.12
4
7.5
0.8
30
0.7
6.2
6.6
5.2
0.35
9
13
2
120
2
0.2
8
0.8
100
–2
1
30
256
12
5
8
2
24
–5
1.015
45
412
14.4
6
9.6
TYP
MAX
36
6.7
7
6
0.6
20
22
7
200
3
0.55
13
1.2
UNITS
V
V
V
V
V
V/µs
V/µs
µA
mV
µs
V
µs
V
mV
µA
V
mV
ms
V
V
V
A
V
dc1717afa
t
G(SWITCHOVER)
Break-Before-Make Time
1
DEMO MANUAL DC1717A
overview
The LTC4417 controls three sets of external back-to-back
P-channel MOSFETs to connect the proper rail to the
load. Precision comparators are used to monitor each of
the three input rails for both UV and OV conditions. The
highest priority input supply whose voltage is within its
respective OV/UV window for at least 256ms is consid-
ered valid and connected to the load. Low signals on the
VALID1, VALID2,
and
VALID3
pins indicate validation of
the V1, V2, and V3 voltages.
DC1717A is designed to operate from inputs of 12V,
5V, and 8V, applied to V1, V2 and V3 respectively. The
valid range of each supply is ±20%, as set by OV and UV
comparators and their associated resistive dividers. V1
has the highest priority, V3 has the lowest. The highest
priority input that is also within its valid range is selected
to power the output. V1, V2 and V3 inputs are protected
against input glitches of up to ±42V. Maximum load cur-
rent is 2A, limited by MOSFET capability.
Logic and LEDs are included to provide visual information
about the operating status. These circuits are powered
from a 6V to 24V auxiliary voltage input (AVI) which is
regulated by an LT3060 (U4) to 5V. This auxiliary 5V rail
also powers 100kΩ pull-ups for
VALID
pins. AVI must be
present in order for the board to operate. See the Modifica-
tion section for a means of eliminating AVI.
operating principles
To eliminate back-and-forth switching during rail switcho-
ver, the LTC4417 provides a 30mV hysteresis in the OV and
UV comparators, and an externally adjustable current mode
hysteresis using the OV/UV resistive dividers. DC1717A’s
input reference hysteresis is 6%, and can be changed to
3% by moving the JP1 jumper to the 30mV position.
The controller’s “break-before-make” switching method
prevents cross conduction between input channels and
reverse current from the output capacitor into the selected
input supply.
Each channel’s control circuit of the LTC4417 has a REV
comparator, which monitors the connecting input supply
and output load voltage. The REV comparator delays the
connection until the output voltage droops 120mV below
the input voltage. This prevents reverse current.
The LTC4417 has two common control pins: EN and
SHDN.
Pulling the EN pin below 1V turns off all external back-to-
back P-channel MOSFETs. When this pin is driven above
1V, the highest priority valid channel is connected to the
load. All these actions are provided without resetting the
256ms OV/UV timers.
Pulling the
SHDN
pin below 0.8V turns off all external
back-to-back P-channel MOSFETs, placing the controller
in a low current state and resetting the 256ms timers
used to validate input rail voltages. It requires at least
256ms to validate each rail voltage after the
SHDN
pin
signal goes high.
The LTC4417 features two different driving modes for the
P-channel MOSFET gates.
One mode is provided by the internal soft-start circuitry,
which limits output voltage slew rate to no more than
5V/ms. As the highest output voltage slew rate, usually, can
impose the highest requirements for circuit components,
5V/ms should be taken into account as a worst case for
component selection.
The soft-start circuitry is enabled each time under the
following conditions:
•
If the LTC4417 is first powered on, or
•
If
SHDN
is forced low, or
•
If V
OUT
falls below ~0.7V
Soft-start is disabled when:
•
any channel turns off, including the channel that is soft
starting.
• 32ms
validation delay time has elapsed during the soft-
start interval.
dc1717afa
2
DEMO MANUAL DC1717A
operating principles
The other driving mode of the P-channel MOSFETs is used
in the voltage switching operation, when the higher priority
rail replaces the rail losing validity. The gate driver oper-
ates with a fixed current, which is defined by the external
component parameters R
S
and C
S
shown in Figure 1.
The LTC4417 circuit designer should select the value of
R
S
and C
S
based on the MOSFET parameters, power rail
source characteristics, acceptable output voltage droop
during transient, and the value of load capacitance.
12V WALL
ADAPTER
V1
M1
C
IN1
68µF
C
VS1
D
S
BAT54
G1
IRF7324
M2
C
S
+
R
S
VS1
LTC4417
V
OUT
+
V
OUT
C
L
47µF
Figure 1
Design proceDure for moDification of Dc1717a
The valid input range for any supply is controlled by the
OV and UV comparators with resistive dividers (R4-R13).
See the LTC4417 data sheet for design equations to select
resistors to match a particular requirement.
Dual MOSFETs, Q1-Q3, may be replaced with single devices
Q4-Q9 by simply removing Q1-Q3. Pads for Q4-Q9 are
located on the bottom side of the board.
The requirement for AVI may be eliminated by removing
jumpers JP2 and JP3, and removing resistor R19. This
modification leaves the LEDs unpowered and the inputs
of U2 and U3 clamp the
VALID
pins at 0.7V, but otherwise
leaves the LTC4417 operating autonomously.
The following design considerations and equations dem-
onstrate the interrelation of the main component values
and transient parameters in the rail transitions, when the
output voltage exceeds 0.7V. The variables C
S
and R
S
used in the design equations correspond to the following
board components:
•
C20, R23 for V1 (+12V channel)
•
C21, R26 for V2 (+5.0V channel)
•
C22, R28 for V3 (+8.0V channel)
To have dominant influence on the transient time C
S
should
be at least ten times larger than the P-channel MOSFET’s
reverse transfer capacitance (Miller). In this design, for
all rails, C
S
(C20, C21,and C22) equals 47nF.
The slew rate of the output voltage can be expressed as
a function of C
S
:
dV
OUT
dV
CS
V
SINK
– | V
THRES
|
=
=
dt
dt
R
S
•
C
S
where:
•
V
SINK
is the LTC4417 parameter rated in the data sheet
as
∆V
G(SINK)
= 4.5V-6V.
•
V
THRES
is the P-channel gate threshold voltage, which
is between –1.5V and –3.5V for the Si7905DN installed
on the board.
•
R
S
= 249Ω and C
S
= 47nF.
Given that dV
OUT
/dt is based on the transient time require-
ment, it is possible to define R
S
from equation 1.
The output voltage slew rate, dV
OUT
/dt, range for the circuit
with the listed parameters is between 85V/ms and 385V/ms.
During the transition of rails, the load can be disconnected
from any rail for a time:
T
DISCON
= t
G(SWITCHOVER)
+ t
pVALID(OFF)
+ t
GATE_THRES
Two first summands of the T
DISCON
are rated in the LTC4417
data sheet as:
t
G(SWITCHOVER)
= (0.3 to 3)µs
t
pVALID(OFF)
= (5 to 13)µs
dc1717afa
(1)
3
DEMO MANUAL DC1717A
Design proceDure for moDification of Dc1717a
The second summand, t
pVALID(OFF)
, should be taken into
account if the associated LTC4417 input does not have
any bypass capacitor and the rail can be disconnected
from the input instantly.
The third one must be calculated as:
⎡ ⎛
V
⎞⎤
THRES
t
GATE _ THRES
=
R
S
•
C
S
⎢
–In
⎜
1–
⎟⎥
V
SINK
⎠⎦
⎣ ⎝
(2)
As shown in the equation (3), the use of external slew rate
control will add additional delay to the total switchover
time. Unfortunately, the actual components cannot be
chosen until the load capacitance is known. This circular
issue can only be resolved through an iterative process.
The process starts by calculating the C
LOAD(MIN)
, assuming
that t
GATE_THRES
=10μs. For clarity this value will be labeled
C
LOAD(INIT)
. Using the calculated C
LOAD(INIT)
, calculate R
S
from the expression of the T
DISCON
. To ensure the newly
calculated R
S
based on C
LOAD(INIT)
is sufficient, calculate
C
LOAD
with the calculated R
S
.
If C
LOAD(INIT)
(the initial calculated C
LOAD
) is higher than
the newly calculated C
LOAD
then the process is completed.
If the C
LOAD(INIT)
is lower than the newly calculated C
LOAD
,
calculate R
S
using the higher value and repeat this process.
It is possible to determine the minimum capacitive load
required to hold the output up during switchover as a:
C
LOAD(MIN)
≥
where:
•
I
LOAD(MAX)
is the maximum load current, A
•
V
OUT(DROOPMAX)
is the maximum acceptable voltage
droop, V
I
LOAD(MAX)
•
T
DISCON
V
OUT(DROOPMAX)
(3)
⎡ ⎛
V
⎞⎤
R
S
•
C
S
⎢
–In
⎜
1–
THRES
⎟⎥ =
10µs
V
SINK
⎠⎦
⎣ ⎝
Calculate R
S
with C
L(INIT)
Recalculate C
L
with R
S
Is recalculated C
L
lower than initial
C
L(INIT)
?
No
Done.
Use C
L(INIT)
and R
S
Figure 2
4
dc1717afa
DEMO MANUAL DC1717A
turrets
V1: 12V supply input; do not exceed ±42V.
V2: 5V supply input; do not exceed ±42V.
V3: 8V supply input; do not exceed ±42V.
GND: Adjacent ground connection for input supplies.
VOUT: Output for up to 2A load.
GND: Adjacent ground connection for load.
AVI: Auxiliary Voltage Input. 6V to 24V input regulated
by U4 to 5V for LEDs, logic and pull ups on various pins.
GND: Adjacent ground connection for auxiliary supply.
5V: 5V regulated output provided by U4, for powering
logic, LEDs and pull ups. Use this turret to verify that 5V
is present.
Each of the following turrets is a direct connection to the
like-name LTC4417 pin:
VALID1:
pulled up with 100kOhm to auxiliary 5V supply.
VALID2:
pulled up with 100kOhm to auxiliary 5V supply.
VALID3:
pulled up with 100kOhm to auxiliary 5V supply.
EN: pulled up by 2μA internal to the LTC4417. Optional
R33 may be added as a pull-up to the auxiliary 5V power
supply.
SHDN:
pulled up by 2μA internal to the LTC4417. Optional
R36 may be added as a pull-up to the auxiliary 5V power
supply.
CAS: used to cascade a second DC1717A. Connect the
CAS turret of the high priority DC1717A to the EN turret
of the lower priority DC1717A.
Grounds must be connected in common.
Jumpers
JP1, HYS: Add 30mV fixed hysteresis to the OV and UV
comparators, or 3% referred to actual supply input. In the
RHYS position input-referred hysteresis is set to 6.4%, as
controlled by R11. Default stuffing position is for 30mV.
JP2, EN: Directly controls EN pin. Default stuffing position
is ON, pulled up by internal 2μA current source.
leDs
No more than one of D8, D9 and D10 will be illuminated
at any given moment:
D8: indicates power is being taken from V1.
D9: indicates power is being taken from V2.
D10: indicates power is being taken from V3.
D11, D16 and D17 indicate the presence of a valid input
on any of the three supplies:
D17: V1 is 12V±20%.
D11: V2 is 5V±20%.
D16: V3 is 8V±20%.
dc1717afa
5
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