Si50122-A3/A4
C
R YS TA L
-
L E S S
PCI-E
XPRESS
G
EN
1 & G
EN
2
D
U A L
O
UTPUT
C
L O C K
G
ENERATOR
Features
Applications
Digital TV
Set top box
Solid State Drives (SSD)
Wireless Access Point
Home Gateway
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Network Attached Storage
Multi-function Printer
Wireless Access Point
Digital Video Cameras
VSS
1
Crystal-less clock generator with
integrated CMEMS
PCI-Express Gen 1/2 compliant
Two PCIe 100 MHz differential
HCSL outputs
One 25 MHz single-ended
LVCMOS output
Supports Serial (ATA) at
100 MHz
Low power differential output
buffers
No termination resistors required
for differential output clocks
Triangular spread spectrum
profile for maximum EMI
reduction (Si50122-A4)
Industrial Temperature –40 to
85 °C
2.5 V, 3.3 V Power supply
Small package 10-pin TDFN
(2.0x2.5 mm)
Si50122-A3 does not support
spread spectrum outputs
Si50122-A4 supports 0.5% down
spread outputs
Ordering Information:
See page 10
Pin Assignments
10
9
8
7
6
VDD
VDD
DIFF2
DIFF2
VSS
REFOUT
NC
2
3
4
DIFF1
Description
DIFF1
5
Si50122-A3/A4 is a high performance, crystal-less PCIe clock generator
that can generate two 100 MHz PCIe clock and one 25 MHz LVCMOS
clock outputs. The differential clock outputs are compliant to PCIe Gen1
and Gen 2 specifications. The ultra-small footprint (2.0x2.5 mm) and
industry leading low power consumption make Si50122-A3/A4 the ideal
clock solution for consumer and embedded applications where board
space is limited and low power is needed.
Patents pending
Functional Block Diagram
VDD
REFOUT
DIFF1
CMEMS
PLL
(SSC)
Divider
DIFF2
VSS
Rev 0.7 9/14
Copyright © 2014 by Silicon Laboratories
Si50122-A3/A4
2
Si50122-A3/A4
Rev 0.7
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Si50122-A3/A4
T
ABLE O F
C
ONTENTS
Section
Page
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Rev 0.7
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3
Si50122-A3/A4
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage (3.3 V Supply)
Supply Voltage (2.5 V Supply)
Symbol
V
DD
V
DD
Test Condition
3.3 V ± 10%
2.5 V ± 10%
Min
2.97
2.25
Typ
3.3
2.5
Max
3.63
2.75
Unit
V
V
Table 2. DC Electrical Specifications
Operating Voltage
VDD=3.3 V
Operating Voltage
VDD=2.5 V
Operating Supply Current
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V
DD
V
DD
I
DD
3.3 V ± 10%
2.97
3.30
2.5
20
18
3
2.5 V ± 10%
2.25
—
—
Full active; 3.3 V ± 10%
Full active; 2.5 V ± 10%
Input Pin Capacitance
C
IN
—
C
OUT
Output Pin Capacitance
—
—
Rev 0.7
Parameter
Symbol
Test Condition
Min
Typ
Max
3.63
2.75
23
21
5
5
Unit
V
V
mA
mA
pF
pF
Input Pin Capacitance
Output Pin Capacitance
4
Si50122-A3/A4
Table 3. AC Electrical Specifications
Parameter
DIFF Clocks
Duty Cycle
Symbol
T
DC
T
SKEW
F
OUT
F
ACC
t
r/f2
V
OX
Condition
Measured at 0 V differential
Measured at 0 V differential
VDD = 3.3 V
All output clocks
Measured differentially from
±150 mV
Min
45
—
—
—
0.6
300
Typ
—
—
100
Max
55
100
—
100
5.0
550
1.15
Unit
%
ps
MHz
ppm
Skew
Output Frequency
Frequency Accuracy
Slew Rate
Crossing Point Voltage at 0.7 V
Swing
Voltage High
Voltage Low
—
—
—
—
V/ns
mV
V
V
%
kHz
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V
HIGH
V
LOW
S
RNG
F
MOD
—
–0.3
—
—
—
–0.5
33
Spread Range
Down Spread, –A4 only
–A4 only
—
Modulation Frequency
PCIe Gen1 Pk-Pk
30
31.5
DIFF Clocks Jitter Parameters, VDD = 3.3 V ± 10%
Pk-Pk
GEN1
RMS
GEN2
PCIe Gen2 Phase Jitter
PCIe Gen 1
—
—
—
20.7
0.8
1.4
35
2.1
2.2
ps
ps
ps
10 kHZ < F < 1.5 MHz
1.5 MHZ < F < Nyquist
PCIe Gen 1
DIFF Clocks Jitter Parameters, VDD = 2.5V ± 10%
PCIe Gen1 Pk-Pk
Pk-Pk
GEN1
RMS
GEN2
PCIe Gen2 Phase Jitter
25 MHz at 3.3 V
Duty Cycle
—
—
—
25
40
2.9
3.0
ps
ps
ps
10 kHZ < F < 1.5 MHz
0.9
1.7
1.5 MHZ < F < Nyquist
Measurement at 1.5 V
T
DC
t
r
t
f
45
—
55
3.0
3.0
250
100
%
ns
ns
Output Rise Time
Output Fall Time
C
L
= 10 pF, 20% to 80%
C
L
= 10 pF, 20% to 80%
Measurement at 1.5 V
Measured at 1.5 V
1.2
1.2
—
—
Cycle to Cycle Jitter
Long Term Accuracy
Powerup Time
Clock Stabilization from Powerup
T
CCJ
L
ACC
T
STABLE
—
—
ps
ppm
First powerup to first output
—
—
10
ms
Note:
Visit www.pcisig.com for complete PCIe specifications.
Rev 0.7
5
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