Si4030/31/32-B1
Si4030/31/32 ISM T
RANSMITTER
Features
Frequency range
240–930 MHz (Si4031/32)
900–960 MHz (Si4030)
Output Power Range
+1 to +20 dBm (Si4032)
–8 to +13 dBm (Si4030/31)
Low Power Consumption
Si4032
85 mA @ +20 dBm
Si4030/31
30 mA @ +13 dBm
Data Rate = 0.123 to 256 kbps
FSK, GFSK, and OOK modulation
Power Supply = 1.8 to 3.6 V
Ultra low power shutdown mode
Wake-up timer
Integrated 32 kHz RC or 32 kHz
XTAL
Integrated voltage regulators
Configurable packet handler
TX 64 byte FIFO
Low battery detector
Temperature sensor and 8-bit ADC
–40 to +85 °C temperature range
Integrated voltage regulators
Frequency hopping capability
On-chip crystal tuning
20-Pin QFN package
Low BOM
Power-on-reset (POR)
Ordering Information:
See page 53.
Pin Assignments
Si4030/31/32
XOUT
nSEL
15 SCLK
14 SDI
13 SDO
12 VDD_DIG
7
GPIO_0
8
GPIO_1
9
GPIO_2
10 11 NC
VR_DIG
nIRQ
SDN
XIN
Applications
Remote control
Home security & alarm
Telemetry
Personal data logging
Toy control
Wireless PC peripherals
Remote meter reading
Remote keyless entry
Home automation
Industrial control
Sensor networks
Health monitors
VDD_RF 1
TX 2
NC 3
NC 4
NC 5
6
NC
20 19 18 17 16
GND
PAD
Description
Silicon Laboratories’ Si4030/31/32 devices are highly integrated, single-chip
wireless ISM transmitters. The high-performance EZRadioPRO
®
family includes a
complete line of transmitters, receivers, and transceivers allowing the RF system
designer to choose the optimal wireless part for their application.
The Si4030/31/32 offers advanced radio features including continuous frequency
coverage from 240–960 MHz with adjustable power output levels of –8 to
+13 dBm on the Si4030/31 and +1 to +20 dBm on the Si4032. Power adjustments
are made in 3 dB steps. The Si4030/31/32’s high level of integration offers
reduced BOM cost while simplifying the overall system design. The Si4032’s
Industry leading +20 dBm output power ensures extended range and improved
link performance.
Additional system features such as an automatic wake-up timer, low battery
detector, 64 byte TX FIFO, and automatic packet handling reduce overall current
consumption and allow the use of lower-cost system MCUs. An integrated
temperature sensor, general purpose ADC, power-on-reset (POR), and GPIOs
further reduce overall system cost and size.
The direct digital transmit modulation and automatic PA power ramping ensure
precise transmit modulation and reduced spectral spreading ensuring compliance
with global regulations including FCC, ETSI, and ARIB regulations.
An easy-to-use calculator is provided to quickly configure the radio settings,
simplifying customer's system design and reducing time to market.
Patents pending
Rev 1.1 1/10
Copyright © 2010 by Silicon Laboratories
Si4030/31/32
Si4030/31/32-B1
Functional Block Diagram
2
Rev 1.1
Si4030/31/32-B1
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1. Modulation Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.2. Modulation Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
5.2. Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
5.4. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
6.1. TX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
6.3. Packet Handler TX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
6.4. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.5. Synchronization Word Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.6. TX Retransmission and Auto TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
7.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
7.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
7.6. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.7. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
9. Application Notes and Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10. Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11. Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12. Pin Descriptions: Si4030/31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Rev 1.1
3
Si4030/31/32-B1
14. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
14.1. Si4030/31/32 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
14.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
15. Package Outline: Si4030/31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
16. PCB Land Pattern: Si4030/31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
4
Rev 1.1
Si4030/31/32-B1
L
IST
OF
F
IGURES
Figure 1. SPI Timing.................................................................................................................. 15
Figure 2. SPI Timing—READ Mode ..........................................................................................16
Figure 3. SPI Timing—Burst Write Mode .................................................................................. 16
Figure 4. SPI Timing—Burst Read Mode .................................................................................. 16
Figure 5. State Machine Diagram.............................................................................................. 17
Figure 6. TX Timing................................................................................................................... 21
Figure 7. Frequency Deviation .................................................................................................. 25
Figure 8. FSK vs. GFSK Spectrums..........................................................................................27
Figure 9. Microcontroller Connections....................................................................................... 30
Figure 10. PLL Synthesizer Block Diagram............................................................................... 31
Figure 11. FIFO Threshold ........................................................................................................34
Figure 12. Packet Structure....................................................................................................... 35
Figure 13. Multiple Packets in TX Packet Handler .................................................................... 36
Figure 14. Operation of Data Whitening, Manchester Encoding, and CRC .............................. 37
Figure 15. Manchester Coding Example ...................................................................................37
Figure 16. POR Glitch Parameters............................................................................................ 39
Figure 17. General Purpose ADC Architecture ......................................................................... 41
Figure 18. Temperature Ranges using ADC8 ........................................................................... 43
Figure 19. WUT Interrupt and WUT Operation.......................................................................... 46
Figure 20. Si4031 Reference Design Schematic ...................................................................... 48
Figure 21. 20-Pin Quad Flat No-Lead (QFN) ............................................................................54
Figure 22. PCB Land Pattern .................................................................................................... 55
Rev 1.1
5
FPGA/CPLD
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