March 1997
NDS8434A
Single P-Channel Enhancement Mode Field Effect Transistor
General Description
SO-8 P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
Features
-7.8 A, -20 V. R
DS(ON)
= 0.024
Ω
@ V
GS
= -4.5 V
R
DS(ON)
= 0.032
Ω
@ V
GS
= -2.5V.
High density cell design for extremely low R
DS(ON).
High power and current handling capability in a widely used
surface mount package.
___________________________________________________________________________________________
5
6
7
4
3
2
1
8
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
T
A
= 25°C unless otherwise noted
NDS8434A
-20
±8
(Note 1a)
Units
V
V
A
W
-7.8
-25
2.5
1.2
1
-55 to 150
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
T
J
,T
STG
R
θ
JA
R
θ
JC
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
50
25
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS8434A Rev.D
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(ON)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= -250 µA
V
DS
= -16 V, V
GS
= 0 V
T
J
=55°C
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
Gate Threshold Voltage
Static Drain-Source On-Resistance
V
GS
= 8 V, V
DS
= 0 V
V
GS
= -8 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= -250 µA
T
J
= 125°C
V
GS
= -4.5 V, I
D
= -7.9 A
T
J
= 125°C
V
GS
= -2.5 V, I
D
= -7.2 A
I
D(on)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
On-State Drain Current
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= -10 V,
I
D
= -7.9 A, V
GS
= -4.5 V
V
DD
= -5 V, I
D
= -1 A,
V
GEN
= -4.5 V, R
GEN
= 6
Ω
V
GS
= -4.5 V, V
DS
= -5 V
V
GS
= -2.5 V, V
DS
= -5 V
V
DS
= -4.5 V, I
D
= -7.9 A
V
DS
= -10 V, V
GS
= 0 V,
f = 1.0 MHz
DYNAMIC CHARACTERISTICS
1730
1100
300
13
38
210
78
35
3.8
8.2
25
70
300
150
55
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
-25
-10
28
S
-0.4
-0.3
-0.51
-0.32
0.021
0.032
0.027
-20
-1
-10
100
-100
-1
-0.8
0.024
0.043
0.032
A
V
µA
µA
nA
nA
V
ON CHARACTERISTICS
(Note 2)
Ω
SWITCHING CHARACTERISTICS
(Note 2)
NDS8434A Rev.D
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
I
S
V
SD
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Parameter
Conditions
Min
Typ
Max
-2.1
Units
A
V
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -2.1 A
(Note 2)
-0.64
-1.2
P
D
(
t
) =
R
θ
JA
(
t
)
T
J
−
T
A
=
R
θ
JC
+
R
θ
C
(
t
)
A
T
J
−
T
A
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 50
o
C/W when mounted on a 1 in
2
pad of 2oz copper.
b. 105
o
C/W when mounted on a 0.04 in
2
pad of 2oz copper.
c. 125
o
C/W when mounted on a 0.006 in
2
pad of 2oz copper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS8434A Rev.D
Typical Electrical Characteristics
-30
V
GS
= -4.5V
I
D
, DRAIN-SOURCE CURRENT (A)
-25
R
DS(on)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
-3.0
-2.5
-2.0
1.8
V
GS
=-2.0V
1.6
-20
1.4
-15
-1.5
-2.5
1.2
-2.7
-10
-3.0
-3.5
-4.5
-5
1
0
0
-0.5
V
DS
-1
-1.5
, DRAIN-SOURCE VOLTAGE (V)
-2
0.8
0
-6
-12
-18
I
D
, DRAIN CURRENT (A)
-24
-30
Figure 1. On-Region Characteristics
.
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage
.
1.6
DRAIN-SOURCE ON-RESISTANCE
R
DS(on)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
1.8
1.4
I
D
= -7.9A
V
GS
= -4.5V
1.6
1.4
1.2
1
0.8
0.6
0.4
0
V
GS
= -4.5V
TJ = 125°C
R
DS(ON)
, NORMALIZED
1.2
25°C
-55°C
1
0.8
0.6
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
-5
-10
I
D
-15
-20
-25
-30
, DRAIN CURRENT (A)
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation
with Drain Current and Temperature
.
V
DS
= -5 V
-20
T
J
= -55°C
V
GS(th)
, NORMALIZED
GATE-SOURCE THRESHOLD VOLTAGE
-25
1.4
1.2
1
0.8
0.6
0.4
0.2
-50
25°C
125°C
V
DS
= V
GS
I
D
=-250µA
I , DRAIN CURRENT (A)
-15
-10
D
-5
0
0
-0.5
-1
-1.5
V
, GATE TO SOURCE VOLTAGE (V)
GS
-2
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 5. Transfer Charateristics
.
Figure 6. Gate Threshold Variation
with Temperature
.
NDS8434A Rev.D
Typical Electrical Characteristics
(continued)
BV
DSS
, NORMALIZED
DRAIN-SOURCE BREAKDOWN VOLTAGE
1.075
1.05
-I
S
, REVERSE DRAIN CURRENT (A)
I
D
= -250µA
20
10
V
GS
= 0V
1
TJ = 125°C
0.1
1.025
25°C
-55°C
1
0.01
0.975
0.001
0.95
-50
0.0001
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0
0.2
0.4
0.6
0.8
1
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 7. Breakdown Voltage
Variation with Temperature.
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature
.
6000
4000
3000
CAPACITANCE (pF)
2000
5
-V
GS
, GATE-SOURCE VOLTAGE (V)
I
D
= -7.9A
4
V
DS
= -5V
-15V
-10V
Ciss
Coss
3
1000
2
500
f = 1 MHz
V
GS
= 0 V
150
0 .1
0 .2
Crss
1
0 .5
1
2
5
-V
, DRAIN TO SOURCE VOLTAGE (V)
DS
10
20
0
0
10
Q
g
20
, GATE CHARGE (nC)
30
40
Figure 9. Capacitance Characteristics
.
Figure 10. Gate Charge Characteristics.
-V
DD
V
IN
D
t
on
t
d(on)
t
r
90%
t
off
t
d(off)
90%
t
f
R
L
V
OUT
DUT
V
GS
V
OUT
10%
R
GEN
10%
90%
G
V
IN
S
10%
50%
50%
PULSE WIDTH
INVERTED
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms
.
NDS8434A Rev.D
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