19-2575; Rev 0; 10/02
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
General Description
The MAX9323 low-skew, low-jitter, clock and data dri-
ver distributes one of two single-ended LVCMOS inputs
to four differential LVPECL outputs. A single logic con-
trol signal (CLK_SEL) selects the input signal to distrib-
ute to all outputs. The device operates from 3.0V to
3.6V, making the device ideal for 3.3V systems, and
consumes only 25mA (max) of supply current.
The MAX9323 features low 150ps part-to-part skew, low
11ps output-to-output skew, and low 1.7ps RMS jitter,
making the device ideal for clock and data distribution
across a backplane or board. All outputs are enabled
and disabled synchronously with the clock input to pre-
vent partial output clock pulses.
The MAX9323 is available in space-saving 20-pin
TSSOP and ultra-small 20-pin 4mm
✕
4mm thin QFN
packages and operates over the extended (-40°C to
+85°C) temperature range. The MAX9323 is pin com-
patible with Integrated Circuit Systems’ ICS8535-01.
o
1.7ps
RMS
Added Random Jitter
o
150ps (max) Part-to-Part Skew
o
11ps Output-to-Output Skew
o
450ps Propagation Delay
o
Pin Compatible with ICS8535-01
o
Consumes Only 25mA (max) Supply Current
(50% Less than ICS8535-01)
o
Synchronous Output Enable/Disable
o
Two Selectable LVCMOS Inputs
o
3.0V to 3.6V Supply Voltage Range
o
-40°C to +85°C Operating Temperature Range
Features
MAX9323
Ordering Information
PART
MAX9323EUP
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
20 TSSOP
Applications
Precision Clock Distribution
Low-Jitter Data Repeater
Data and Clock Driver and Buffer
Central-Office Backplane Clock Distribution
DSLAM Backplane
Base Station
Hubs
MAX9323ETP*
-40°C to +85°C
20 Thin QFN-EP**
*Future
product—Contact factory for availability.
**EP
= Exposed paddle.
Functional Diagram and Typical Operating Circuit appear at
end of data sheet.
Pin Configurations
CLK_SEL
CLK_EN
GND
Q0
17
Q0
16
GND 1
CLK0 1
N.C. 2
CLK1 3
N.C. 4
N.C. 5
15 V
CC
14 Q1
CLK_EN 2
CLK_SEL 3
CLK0 4
N.C. 5
12 Q2
11 Q2
CLK1 6
N.C. 7
N.C. 8
6
N.C.
7
V
CC
8
Q3
9
Q3
10
V
CC
N.C. 9
V
CC
10
12 Q3
11 Q3
20 Q0
19 Q0
18 V
CC
17 Q1
TOP VIEW
20
19
18
MAX9323
**EXPOSED PADDLE
13 Q1
MAX9323
16 Q1
15 Q2
14 Q2
13 V
CC
THIN QFN-EP** (4mm x 4mm)
**CONNECT EXPOSED PADDLE TO GND.
TSSOP
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
MAX9323
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND ...........................................................-0.3V to +4.0V
Q_,
Q_,
CLK_, CLK_SEL,
CLK_EN to GND .....................................-0.3V to (V
CC
+ 0.3V)
Continuous Output Current .................................................50mA
Surge Output Current........................................................100mA
Continuous Power Dissipation (T
A
= +70°C)
20-Pin TSSOP (derate 11mW/°C)..............................879.1mW
20-Pin 4mm
✕
4mm Thin QFN (derate 16.9mW/°C)...1349.1mW
Junction-to-Ambient Thermal Resistance in Still Air
20-Pin TSSOP ............................................................+91°C/W
20-Pin 4mm
✕
4mm Thin QFN.................................+59.3°C/W
Junction-to-Case Thermal Resistance
20-Pin TSSOP ............................................................+20°C/W
20-Pin 4mm
✕
4mm Thin QFN......................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature (10s) ...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0V to 3.6V, outputs terminated with 50Ω ±1% to (V
CC
- 2V), CLK_SEL = V
CC
or GND, CLK_EN = V
CC
, T
A
= -40°C to +85°C,
unless otherwise noted. Typical values are at V
CC
= 3.3V, T
A
= +25°C.) (Notes 1, 2, and 3)
PARAMETER
SYMBOL
CONDITIONS
CLK0, CLK1
CLK_EN, CLK_SEL
CLK0, CLK1
CLK_EN, CLK_SEL
MIN
2
2
0
0
-5
-5
-150
4
V
CC
-
1.4
V
CC
-
2.0
0.6
V
CC
-
1.0
V
CC
-
1.7
0.85
25
TYP
MAX
V
CC
V
CC
1.3
0.8
150
+5
+5
UNITS
INPUTS (CLK0, CLK1, CLK_SEL, CLK_EN)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Capacitance
OUTPUTS (Q_,
Q_)
Single-Ended Output High
Voltage
Single-Ended Output Low
Voltage
Differential Output Voltage
SUPPLY
Supply Current (Note 5)
I
CC
mA
V
OH
V
OL
V
OD
Figure 1
Figure 1
Figure 1, V
OD
= V
OH
- V
OL
V
V
V
V
IH
V
IL
I
IH
I
IL
C
IN
Figure 1
Figure 1
V
V
µA
µA
pF
CLK0, CLK1, CLK_SEL = V
CC
CLK_EN = V
CC
CLK0, CLK1, CLK_SEL = GND
CLK_EN = GND
CLK0, CLK1, CLK_SEL, CLK_EN (Note 4)
2
_______________________________________________________________________________________
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.0V to 3.6V, outputs terminated with 50Ω ±1% to (V
CC
-2V), f
IN
< 266MHz, input duty cycle = 50%, input transition time =
1.1ns (20% to 80%), V
IH
= V
CC
, V
IL
= GND, CLK_SEL = V
CC
or GND, CLK_EN = V
CC
, T
A
= -40°C to +85°C, unless otherwise noted.
Typical values are at V
CC
= 3.3V, T
A
= +25°C.) (Note 4)
PARAMETER
Switching Frequency
Propagation Delay
Output-to-Output Skew
Part-to-Part Skew
Output Rise Time
Output Fall Time
Output Duty Cycle
Added Random Jitter
Added Jitter (Note 9)
SYMBOL
f
MAX
t
PHL
, t
PLH
t
SKOO
t
SKPP
t
R
t
F
ODC
t
RJ
t
AJ
f
IN
= 266MHz, clock pattern (Note 9)
V
CC
= 3.3V with 25mV superimposed
sinusoidal noise at 100kHz
CONDITIONS
V
OH
- V
OL
≥
0.6V
V
OH
- V
OL
≥
0.3V
CLK0 or CLK1 to Q_,
Q_,
Figure 1 (Note 6)
(Note 7)
(Note 8)
20% to 80%, Figure 1
80% to 20%, Figure 1
100
100
48
203
198
50
1.7
MIN
266
1500
100
450
600
30
150
300
300
52
3
10
TYP
800
MAX
UNITS
MHz
ps
ps
ps
ps
ps
%
ps
(RMS)
ps
(P-P)
MAX9323
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Measurements are made with the device in thermal equilibrium.
Positive current flows into a pin. Negative current flows out of a pin.
DC parameters are production tested at T
A
= +25°C and guaranteed by design over the full operating temperature range.
Guaranteed by design and characterization. Limits are set at ±6 sigma.
All pins open except V
CC
and GND.
Measured from the 50% point of the input to the crossing point of the differential output signal.
Measured between outputs of the same part at the differential signal crosspoint for a same-edge transition.
Measured between outputs of different parts at the differential signal crosspoint under identical conditions for a same-edge
transition.
Note 9:
Jitter added to the input signal.
_______________________________________________________________________________________
3
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
MAX9323
Typical Operating Characteristics
(V
CC
= 3.3V, outputs terminated to (V
CC
- 2V) through 50Ω, CLK_SEL = V
CC
or GND, CLK_EN = V
CC
, T
A
= +25°C.)
OUTPUT AMPLITUDE (V
OH
- V
OL
)
vs. FREQUENCY
MAX9323 toc01
SUPPLY CURRENT vs. TEMPERATURE
14.0
13.5
SUPPLY CURRENT (mA)
13.0
12.5
12.0
11.5
11.0
10.5
10.0
-40
-15
10
35
60
85
TEMPERATURE (°C)
800
700
OUTPUT AMPLITUDE (mV)
600
500
400
300
200
100
0
0
200 400 600 800 1000 1200 1400 1600
FREQUENCY (MHz)
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9323 toc03
PROPAGATION DELAY
vs. TEMPERATURE
490
PROPAGATION DELAY (ps)
480
470
460
450
440
430
420
410
400
t
PHL
t
PLH
MAX9323 toc04
230
220
OUTPUT RISE/FALL TIME (ps)
210
200
190
180
170
160
150
140
-40
-15
10
35
60
t
F
t
R
500
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
MAX9323 toc02
One-to-Four LVCMOS-to-LVPECL
Output Clock and Data Driver
Pin Description
PIN
TSSOP
1
QFN
18
NAME
GND
FUNCTION
Ground. Provide a low-impedance connection to the ground plane.
Synchronous Output Enable. Connect CLK_EN to V
CC
or leave floating to enable the
differential outputs. Connect CLK_EN to GND to disable the differential outputs. When
disabled, Q_ asserts low and
Q_
asserts high. An internal 51kΩ pullup resistor to V
CC
allows
CLK_EN to be left floating.
Clock Select Input. Connect CLK_SEL to V
CC
to select the CLK1 input. Connect CLK_SEL to
GND or leave floating to select the CLK0 input. Only the selected CLK_ signal is reproduced
at each output. An internal 51kΩ pulldown resistor to GND allows CLK_SEL to be left floating.
LVCMOS Clock Input. When CLK_SEL = GND, each set of outputs differentially reproduces
CLK0. An internal 51kΩ pulldown resistor to GND forces the outputs (Q_,
Q_)
to differential low
when CLK0 is left open or at GND, CLK_SEL = GND, and the outputs are enabled.
No Connect. Not internally connected.
LVCMOS Clock Input. When CLK_SEL = V
CC
, each set of outputs differentially reproduces
CLK1. An internal 51kΩ pulldown resistor to GND forces the outputs (Q_,
Q_)
to differential low
when CLK1 is left open or at GND, CLK_SEL = V
CC
, and the outputs are enabled.
Positive Supply Voltage. Bypass V
CC
to GND with three 0.01µF and one 0.1µF ceramic
capacitors. Place the 0.01µF capacitors as close to each V
CC
input as possible (one per V
CC
input). Connect all V
CC
inputs together, and bypass to GND with a 0.1µF ceramic capacitor.
Inverting Differential LVPECL Output. Terminate
Q3
to (V
CC
- 2V) with a 50Ω ±1% resistor.
Noninverting Differential LVPECL Output. Terminate Q3 to (V
CC
- 2V) with a 50Ω ±1% resistor.
Inverting Differential LVPECL Output. Terminate
Q2
to (V
CC
- 2V) with a 50Ω ±1% resistor.
Noninverting Differential LVPECL Output. Terminate Q2 to (V
CC
- 2V) with a 50Ω ±1% resistor.
Inverting Differential LVPECL Output. Terminate
Q1
to (V
CC
- 2V) with a 50Ω ±1% resistor.
Noninverting Differential LVPECL Output. Terminate Q1 to (V
CC
- 2V) with a 50Ω ±1% resistor.
Inverting Differential LVPECL Output. Terminate
Q0
to (V
CC
- 2V) with a 50Ω ±1% resistor.
Noninverting Differential LVPECL Output. Terminate Q0 to (V
CC
- 2V) with a 50Ω ±1% resistor.
MAX9323
2
19
CLK_EN
3
20
CLK_SEL
4
5, 7, 8, 9
6
1
2, 4, 5, 6
3
CLK0
N.C.
CLK1
10, 13, 18
11
12
14
15
16
17
19
20
7, 10, 15
8
9
11
12
13
14
16
17
V
CC
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
Detailed Description
The MAX9323 low-skew, low-jitter, clock and data dri-
ver distributes one of two single-ended LVCMOS input
signals to four differential LVPECL outputs. An input
multiplexer allows selection of one of the two input sig-
nals. The output drivers operate at frequencies up to
1.5GHz. The MAX9323 operates from 3.0V to 3.6V,
making it ideal for 3.3V systems.
select CLK0. Connect CLK_SEL to V
CC
to select CLK1.
CLK0 and CLK1 are pulled to GND through internal
51kΩ resistors, when not connected.
CLK_EN Input
CLK_EN enables/disables the differential outputs of the
MAX9323. Connect CLK_EN to V
CC
to enable the differ-
ential outputs. The (Q_,
Q_)
outputs are driven to a differ-
ential low condition when CLK_EN = GND. Each
differential output pair disables following successive ris-
ing and falling edges on CLK_, after CLK_EN connects to
GND. Both a rising and falling edge on CLK_ are required
to complete the enable/disable function (Figure 2).
Data Inputs
Single-Ended LVCMOS Inputs
The MAX9323 accepts two single-ended LVCMOS
inputs (CLK0 and CLK1, Figure 1). An internal refer-
ence (V
CC
/2) provides the input thresold voltage for
CLK0 and CLK1. CLK_SEL selects the CLK0 input or
CLK1 input to be converted to four differential LVPECL
signals (see Table 1). Connect CLK_SEL to GND to
CLK_SEL Input
CLK_SEL selects which single-ended LVCMOS input
signal is output differentially as four LVPECL signals.
Connect CLK_SEL to GND to select the CLK0 input.
5
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