1518
5-TAP SMD DELAY LINE
T
D
/T
R
= 3
(SERIES 1518)
FEATURES
•
•
•
•
•
5 taps of equal delay increment
Delays to 200ns
Low profile
Epoxy encapsulated
Meets or exceeds MIL-D-23859C
IN
N/C
T2
N/C
T4
T5
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
N/C
T1
N/C
T3
N/C
N/C
N/C
data
3
®
delay
devices,
inc.
PACKAGES
IN
Signal Input
T1-T5 Tap Outputs
GND Ground
Note: Standard pinout shown
Alt. pinout available
FUNCTIONAL DESCRIPTION
The 1518-series device is a fixed, single-input, five-
output, passive delay line. The signal input (IN) is
reproduced at the outputs (T1-T5) in equal increments.
The delay from IN to T5 (T
D
) and the characteristic
impedance of the line (Z) are determined by the dash
number. The rise time (T
R
) of the line is 30% of T
D
, and
the 3dB bandwidth is given by 1.05 / T
D
. The device is
available in a 14-pin SMD with two pinout options.
Part numbers are constructed according to the scheme
shown at right. For example, 1518-101-500A is a 100ns,
50Ω delay line with pinout code A. Similarly, 1518-151-
501 a is 150ns, 500Ω delay line with standard pinout.
PART NUMBER CONSTRUCTION
1518 - xxx - zzz p
DELAY TIME
Expressed in nanoseconds (ns)
First two digits are significant figures
Last digit specifies # of zeros to follow
IMPEDANCE
Expressed in nanoseconds (ns)
First two digits are significant figures
Last digit specifies # of zeros to follow
PINOUT CODE
See Table
Omit for STD pinout
SERIES SPECIFICATIONS
•
•
•
•
•
Dielectric breakdown:
Distortion @ output:
Operating temperature:
Storage temperature:
Temperature coefficient:
50 Vdc
10% max.
-55°C to +125°C
-55°C to +125°C
100 PPM/°C
T
D
(ns)
5
10
15
20
25
30
40
50
60
75
80
100
110
125
150
180
200
DELAY SPECIFICATIONS
T
I
(ns)
1.0
2.0
3.0
4.0
5.0
6.0
8.0
10.0
12.0
15.0
16.0
20.0
22.0
25.0
30.0
36.0
50.0
T
R
(ns)
3.0
4.0
5.0
6.0
7.0
10.0
13.0
15.0
20.0
25.0
26.0
30.0
32.0
40.0
50.0
60.0
70.0
Z=50Ω
Ω
N/A
3
3
3
3
3
3
3
3
3
4
4
4
4
N/A
N/A
N/A
ATTENUATION (%) TYPICAL
Z=100Ω Z=200Ω Z=300Ω Z=500Ω
Ω
Ω
Ω
Ω
5
N/A
N/A
N/A
5
5
N/A
N/A
5
5
N/A
N/A
5
5
5
N/A
5
5
5
7
5
5
5
7
5
5
5
7
5
5
7
7
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
8
10
10
7
8
10
10
8
10
12
12
T1 T2 T3 T4
IN
GND
T5
GND
Functional Diagram
.018
.505
.050
.185
14
8
Notes: T
I
represents nominal tap-to-tap delay increment
Tolerance on T
D
=
±
5% or
±
2ns, whichever is greater
Tolerance on T
I
=
±
5% or
±
1ns, whichever is greater
“N/A” indicates that delay is not available at this Z
.425
.290
1
7
PINOUT CODES
CODE
STD
A
IN
1
1
T1
13
12
T2
3
4
T3
11
10
T4
5
6
T5
6
7
GND
7
8,14
.300
.100
Package Dimensions
©
1997 Data Delay Devices
Doc #97030
2/7/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
FPGA/CPLD
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