ADVANCE INFORMATION
ICRO
C
LOCK
Description
The MK2049-02 is a Phase-Locked Loop (PLL)
based clock synthesizer that accepts multiple input
frequencies. With an 8 kHz clock input as a
reference, the MK2049-02 generates T1, E1, T3,
E3, and other communications frequencies. This
allows for the generation of clocks frequency-
locked to an 8 kHz backplane clock, simplifying
clock synchronization in communications systems.
The MK2049-02 can also accept a T1, E1, T3, or
E3 input clock and provide the same output for
loop timing, and has a “jitter-attenuated” buffer
capability. All outputs are frequency locked
together and to the input.
In the Buffer Mode, the MK2049-02 is ideal for
filtering jitter from 27 MHz video clocks or other
clocks with high jitter.
ICS/MicroClock can customize this device for
many other different frequencies. Contact your
ICS/MicroClock representative for more details.
MK2049-02
Communications Clock PLL
Features
• Packaged in 20 pin SOIC
• Fixed input-output phase relationship
• Accepts multiple inputs: 8 kHz backplane clock,
Loop Timing frequencies, or 10-28 MHz
• Locks to 8 kHz ±100 ppm (External mode)
• Buffer Mode allows jitter attenuation of
10–28 MHz input and x1/x0.5 or x2/x4 outputs
• Exact ratios stored in the device eliminate the need
for external dividers
• Patented design gives zero ppm synthesis error in
all output clocks
• Output clock rates include T1, E1, T3, E3, and
OC3 submultiples
• Low jitter designed to meet ANSI specifications
• 5V ±10% operation
Block Diagram
VDD GND
FS3:0
4
PLL
Clock
Synthesis,
Control, and
De-jitter
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
CLK1
Clock
Input
Reference
X1
Crystal
External/
Loop Timing
Mux
CLK2
Crystal
Oscillator
8 kHz
(External
Mode only)
X2
CAP1
CAP2
1
Revision 7309
Printed 7/30/99
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel•(408)295-9818fax
MDS2049-02
ADVANCE INFORMATION
ICRO
C
LOCK
Pin Assignment
FS1
X2
X1
VDD
VDD
VDD
GND
CLK2
CLK1
8K
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
FS0
RESET
CAP2
GND
CAP1
VDD
GND
ICLK
FS3
FS2
MK2049-02
Communications Clock PLL
20 pin (300 mil) SOIC
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
FS1
X2
X1
VDD
VDD
VDD
GND
CLK2
CLK1
8K
FS2
FS3
ICLK
GND
VDD
CAP1
GND
CAP2
RESET
FS0
Type
I
XO
XI
P
P
P
P
O
O
O
I
I
I
P
P
LF
P
LF
I
I
Description
Frequency Select 1. Determines CLK input/outputs per tables on page 3.
Crystal connection. Connect to a MHz crystal as shown in the tables on page 3.
Crystal connection. Connect to a MHz crystal as shown in the tables on page 3.
Connect to +5V.
Connect to +5V.
Connect to +5V.
Connect to ground.
Clock 2 output determined by status of FS3:0 per tables on page 3.
Clock 1 output determined by status of FS3:0 per tables on page 3. Always equals 1/2 of CLK2.
Recovered 8 kHz clock output. On External Mode only.
Frequency Select 2. Determines CLK input/outputs per tables on page 3.
Frequency Select 3. Determines CLK input/outputs per tables on page 3.
Input clock connection. Connect to 8 kHz backplane or MHz clock.
Connect to ground.
Connect to +5V.
Connect the loop filter ceramic capacitors and resistor between this pin and CAP2.
Connect to ground.
Connect the loop filter ceramic capacitors and resistor between this pin and CAP1.
Reset pin. Resets internal PLL when low. Outputs will stop low.
Frequency Select 0. Determines CLK input/outputs per tables on page 3.
Type: XI, XO = crystal connections, I = Input, O = output, P = power supply connection, LF = loop filter
connections
2
Revision 7309
Printed 7/30/99
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel•(408)295-9818fax
MDS2049-02
ADVANCE INFORMATION
ICRO
C
LOCK
Output Decoding Table – External Mode (MHz)
ICLK
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
CLK1
1.544
2.048
22.368
17.184
19.44
16.384
24.576
25.92
10.24
4.096
CLK2
3.088
4.096
44.736
34.368
38.88
32.768
49.152
51.84
20.48
8.192
Crystal
12.352
12.288
11.184
11.456
12.96
8.192
12.288
12.96
10.24
12.288
MK2049-02
Communications Clock PLL
Zero Delay
ICLK to CLK2
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Output Decoding Table – Loop Timing Mode (MHz)
ICLK
1.544
2.048
44.736
34.368
FS3 FS2 FS1 FS0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
CLK1
1.544
2.048
22.368
17.184
CLK2
3.088
4.096
44.736
34.368
Crystal
12.352
12.288
11.184
11.456
Zero Delay
ICLK to CLK2
No
No
Yes
Yes
Output Decoding Table – Buffer Mode (MHz)
ICLK
19 - 28
10 - 14
FS3 FS2 FS1 FS0
1
1
1
1
1
1
0
1
CLK1
ICLK/2
2*ICLK
CLK2
ICLK
4*ICLK
Zero Delay
ICLK to CLK2
ICLK/2
Yes
ICLK
Yes
Crystal
• 0 = connect directly to ground, 1 = connect directly to VDD.
• Crystal is connected to pins 2 and 3; clock input is applied to pin
13.
Operating Modes
The MK2049-02 has three operating modes: External, Loop Timing, and Buffer. Although each mode
uses an input clock to generate various output clocks, there are important differences in their input and
crystal requirements.
External Mode
The MK2049-02 accepts an external 8 kHz clock and will produce a number of common communication
clock frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse
as narrow as 10 ns is acceptable.
Loop Timing Mode
This mode can be used to remove the jitter from a high-frequency input clock. For T1 and E1 inputs, the
CLK1 output will be the same as the input frequency, with CLK2 at twice the input frequency. For T3
and E3 inputs, CLK1 will be 1/2 the input frequency and CLK2 will be the same as the input frequency.
3
Revision 7309
Printed 7/30/99
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel•(408)295-9818fax
MDS2049-02
ADVANCE INFORMATION
ICRO
C
LOCK
Operating Modes (continued)
MK2049-02
Communications Clock PLL
Buffer Mode
Unlike the other two modes that accept only a single specified input frequency, Buffer Mode will accept a
wider range of input clocks. The input jitter is attenuated, and the outputs on CLK1 and CLK2 also
provide the option of getting x1, x2, x4, or 1/2 of the input frequency. For example, this mode can be
used to remove the jitter from a 27 MHz clock, generating low-jitter 27 MHz and 13.5 MHz outputs.
Input And Output Synchronization
As shown in the tables on page 3, the MK2049-02 offers a Zero Delay feature in most selections. In these
selections, there is an internal feedback path between ICLK and the CLK2 output clock. This provides a
fixed phase relationship between the input and output, a requirement in many communications systems.
As shown in the diagram below, when using one of the Zero Delay selections, the rising edge of ICLK will
be aligned with the rising edge of CLK2. However, the CLK1 edge in these cases will be either rising or
falling. (8 kHz is used in this illustration, but the same is true for the Zero Delay selections with MHz
inputs.)
ICLK (8 kHz)
CLK2 (MHz)
CLK1 (MHz)
Figure 1. Input and Output Clock Waveforms in Zero Delay Selections
In the modes that are not Zero Delay, the phase relationship between the input and output clocks is not
predictable. Although it will not change once the MK2049-02 is running, this relationship may change
when power is interrupted.
In all modes, the output frequencies are locked to the input, and will remain at the specified output
frequency, as long as the combined variation of the input frequency and the crystal does not exceed
100 ppm. For example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the
input frequency can vary by up to 60 ppm and still have the output frequency remain locked.
4
Revision 7309
Printed 7/30/99
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel•(408)295-9818fax
MDS2049-02
ADVANCE INFORMATION
ICRO
C
LOCK
External Components/Crystal Selection
MK2049-02
Communications Clock PLL
The MK2049-02 requires a minimum number of external components for proper operation. A decoupling
capacitor of 0.01µF must be connected between VDD and GND pins close to the chip (especially pins 4
and 7, 15 and 17), and 33
Ω
terminating resistors can be used on clock outputs with traces longer than 1
inch (assuming 50
Ω
traces). The external loop filter should be connected between CAP1 and CAP2 as
shown below, and as close to the chip as possible. High quality ceramic capacitors are recommended, but
leave provisions for sizes up to 10µF. See also the section titled “Loop Bandwidth and Loop Filter
Component Selection” on page 9 for more details on these components.
CAP2
CAP1
External crystal capacitors may be needed to tune the crystal frequency; leave pads for these capacitors on
the layout. The crystal should be a fundamental, parallel mode, AT cut pullable crystal with 14 pF load
capacitance. Refer to the table below for additional specifications on the crystal.
Crystal Specifications
Parameter
Operating Temperature Range
Nominal Frequency
Initial Accuracy at 25 C
Temperature stability
Aging, first year
Aging, 10 years
Load Capacitance
Shunt Capacitance, C0
Motional Capacitance, C1
C0/C1 ratio for 12.288 MHz - 12.96 MHz*
Minimum
Typical
Maximum
0
25
70
As stated in the tables on Page 3
-20
20
-30
30
-5
5
-20
20
14
7
none
none
250
Units
C
MHz
ppm
ppm
ppm
ppm
pF
pF
pF
none
*This ratio decreases for lower crystal frequencies.
Crystal Part Numbers from Ecliptek (http://www.ecliptek.com)
Frequency
8.192
10.24
11.184
11.456
12.288
12.352
12.96
MDS2049-02
Ecliptek P/N
ECX-5225-8.192M
ECX-5226-10.24M
ECX-4901-11.184M
ECX-4902-11.456M
ECX-4735-12.288M
ECX-4904-12.352M
ECX-4903-12.96M
5
Revision 7309
Printed 7/30/99
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel•(408)295-9818fax
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