Intel
®
80321 I/O Processor
Datasheet
Product Features
s
s
s
s
Core Features
— Integrated Intel
®
XScale
™
Core
— ARM* V5T Instruction Set
— ARM V5E DSP Extensions
— 400 MHz and 600 MHz
— Write Buffer, Write-back Cache
PCI Bus Interface
—
PCI Local Bus Specification,
Rev. 2.2
compliant
—
PCI-X Addendum to the PCI Local Bus
Specification,
Rev. 1.0a
— 64-bit/66MHz Operation in PCI Mode
—64-bit/133MHz Operation in PCI-X Mode
— Support 32-bit PCI Initiators and Targets
— Four Split Read Requests as Initiator
— Eight Split Read Requests as Target
— 64-bit Addressing Support
Memory Controller
—PC200 Double Data Rate (DDR) SDRAM
— Up to 1 GB of 64-bit DDR SDRAM
— Up to 512 MB of 32-bit DDR SDRAM
— Single-bit Error Correction, Multi-bit
Support (ECC)
— 1024-byte Posted Memory Write Queue
— 40- and 72-bit wide Memory Interface
Address Translation Unit
— 2 KB or 4 KB Outbound Read Queue
— 4 KB Outbound Write Queue
— 4 KB Inbound Read and Write Queue
—Connects Internal Bus to PCI/PCI-X Bus
s
s
s
s
s
s
s
s
DMA Controller
— Two Independent Channels Connected
to Internal Bus
— Up to 1064 MB/s Burst Support in
PCI-X Mode
— Up to 1600 MB/s Burst Support for
Internal Bus
— Two 1-KB Queues in Ch-0 and Ch-1
— 2
32
Addressing Range on Internal Bus
Interface
— 2
64
Addressing Range on PCI Interface
Application Accelerator Unit
— Performs XOR on Read Data
— Compute Parity Across Local Memory
Blocks
— 1 KB/512-byte Store Queue
I
2
C Bus Interface Units
— Two Separate I
2
C Units
— Serial Bus
— Master/Slave Capabilities
— System Management Functions
SSP Serial Port
— Full-duplex Synchronous Serial Interface
— Supports 7.2 KHz to 1.84 MHz Bit Rates
Peripheral Performance Monitoring Unit
— One Dedicated Global Time Stamp
Counter
— Fourteen Programmable Event Counters
— Three Control/Status Registers
Timers
— Two Dual-programmable 32-bit Timers
— Watchdog Timer
544-Ball, Plastic Ball Grid Array (PBGA)
Eight General Purpose I/O Pins
Document Number: 273518-002
June 2002
Intel® 80321 I/O Processor
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The
Intel
®
Intel
®
80321 I/O Processor
may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Intel
®
internal code names are subject to change.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright© Intel Corporation, 2002
AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic,
DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740,
IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel
NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation,
Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer
logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare,
RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In,
TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and
other countries.
*Other names and brands may be claimed as the property of others.
2
June 2002
Datasheet
Intel® 80321 I/O Processor
Contents
1.0
Introduction......................................................................................................................... 7
1.1
About This Document............................................................................................7
1.1.1 Terminology..............................................................................................7
1.1.2 Other Relevant Documents ...................................................................... 8
About the Intel
®
80321 I/O Processor ................................................................... 9
1.2
2.0
Features ...........................................................................................................................11
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
Internal Bus ......................................................................................................... 11
DMA Controller.................................................................................................... 11
Address Translation Unit .....................................................................................12
Messaging Unit.................................................................................................... 12
Memory Controller............................................................................................... 12
Peripheral Bus Interface...................................................................................... 12
Application Accelerator Unit ................................................................................ 13
Performance Monitoring Unit............................................................................... 13
I
2
C Bus Interface Units ........................................................................................ 13
Synchronous Serial Port Unit ..............................................................................13
3.0
Package Information ........................................................................................................14
3.1
Package Introduction........................................................................................... 14
3.1.1 Functional Signal Definitions ..................................................................14
3.1.2 544-Lead PBGA Package ...................................................................... 25
Package Thermal Specifications .........................................................................39
3.2.1 Thermal Specifications ........................................................................... 39
3.2.1.1 Ambient Temperature................................................................ 39
3.2.1.2 Case Temperature .................................................................... 39
3.2.1.3 Thermal Resistance ..................................................................39
3.2.2 Thermal Analysis .................................................................................... 40
Socket Information .............................................................................................. 41
3.3.1 Socket-Header Vendor........................................................................... 41
3.3.2 Burn-in Socket Vendor ........................................................................... 41
3.3.3 Shipping Tray Vendor............................................................................. 41
3.3.4 Logic Analyzer Interposer Vendor .......................................................... 41
3.3.5 JTAG Emulator Vendor .......................................................................... 42
3.2
3.3
4.0
Electrical Specifications.................................................................................................... 43
4.1
4.2
4.3
4.4
Absolute Maximum Ratings................................................................................. 43
V
CCPLL
Pin Requirements ................................................................................... 43
Targeted DC Specifications................................................................................. 44
Targeted AC Specifications................................................................................. 46
4.4.1 Clock Signal Timings ..............................................................................46
4.4.2 PCI Interface Signal Timings ..................................................................47
4.4.3 DDR SDRAM Interface Signal Timings .................................................. 48
4.4.4 Peripheral Bus Interface Signal Timings ................................................ 48
4.4.5 I
2
C Interface Signal Timings................................................................... 48
4.4.6 SSP Interface Signal Timings................................................................. 49
4.4.7 Boundary Scan Test Signal Timings ...................................................... 50
AC Timing Waveforms ........................................................................................ 51
AC Test Conditions ............................................................................................. 55
June 2002
3
4.5
4.6
Datasheet
Intel® 80321 I/O Processor
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Intel
®
80321 I/O Processor Functional Block Diagram ....................................... 10
544-Lead PBGA Package (Top View)................................................................. 25
544-Lead PBGA Package (Bottom View) ........................................................... 26
Ball Map - Left Side - Top View........................................................................... 27
Ball Map - Right Side - Top View ........................................................................ 28
Thermocouple Attachment - No Heatsink ........................................................... 39
V
CCPLL
Lowpass Filter ........................................................................................ 43
Clock Timing Measurement Waveforms ............................................................. 51
Output Timing Measurement Waveforms ........................................................... 51
Input Timing Measurement Waveforms .............................................................. 52
I
2
C Interface Signal Timings................................................................................ 52
DDR SDRAM Write Timings ............................................................................... 53
DDR SDRAM Read Timings ............................................................................... 54
AC Test Load for all Signals Except PCI and DDR SDRAM ............................... 55
PCI/PCI-X TOV(max) Rising Edge AC Test Load............................................... 55
PCI/PCI-X TOV(max) Falling Edge AC Test Load .............................................. 55
PCI/PCI-X TOV(min) AC Test Load .................................................................... 56
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Related Documentation......................................................................................... 8
Pin Description Nomenclature............................................................................. 14
DDR SDRAM Signals.......................................................................................... 15
Peripheral Bus Interface Signals ......................................................................... 16
PCI Bus Signals .................................................................................................. 19
Serial Port Interface Signals................................................................................ 20
Miscellaneous Signals......................................................................................... 21
Pin Mode Behavior .............................................................................................. 23
544-Lead PBGA Package - Alphabetical Ball Listing .......................................... 29
544-Lead PBGA Package - Alphabetical Signal Listing ...................................... 34
544-Lead PBGA Package Thermal Characteristics ............................................ 40
Socket-Header Vendor........................................................................................ 41
Burn-in Socket Vendor ........................................................................................ 41
Shipping Tray Vendor ......................................................................................... 41
Logic Analyzer Interposer Vendor ....................................................................... 41
JTAG Emulator Vendor ....................................................................................... 42
Operating Conditions .......................................................................................... 43
DC Characteristics .............................................................................................. 44
I
CC
Characteristics .............................................................................................. 45
Clock Timings...................................................................................................... 46
PCI Signal Timings.............................................................................................. 47
DDR SDRAM Signal Timings .............................................................................. 48
Peripheral Bus Signal Timings ............................................................................ 48
I
2
C Signal Timings............................................................................................... 48
SSP Signal Timings ............................................................................................ 49
Boundary Scan Test Signal Timings ................................................................... 50
DAT Mode Timings ............................................................................................. 50
Bypass Mode Timings ......................................................................................... 50
AC Measurement Conditions .............................................................................. 55
4
June 2002
Datasheet
Intel® 80321 I/O Processor
Revision History
Date
June 2002
February 2002
Revision #
002
001
Description
Removed Advance Information designation.
Initial release.
Datasheet
June 2002
5
GD32 MCU
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