Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Datasheet - Commercial and Extended Temperature (80200T)
Product Features
I
I
I
I
High Performance Processor based on
Intel
®
XScale
™
Microarchitecture
— 7-8 stage Intel
®
Superpipelined
Technology
— 32-Entry Instruction Memory
Management Unit
— 32-Entry Data Memory Management
Unit
— 32 KByte, 32-way Set Associative
Instruction Cache
— 32 KByte, 32-way Set Associative Data
Cache
— 2 KByte, 2-way Set Associative
Mini-Data Cache
— 128-Entry Branch Target Buffer
— 8-Entry Write Buffer
— 4-Entry Fill and Pend Buffers
Intel
®
Dynamic Voltage Management
— Core Voltage Range: 0.95 V to 1.55 V
— Internal Clock Scalable by Software
— Input Clock: 33-66 MHz
ARM* Version 5TE Compliant
Application-Code Compatible with
Intel
®
StrongARM* SA-110
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I
I
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Power Management
— Core Power is ~500mW at 600MHz
— Core Voltage Operation Down to 0.95 V
— Idle and Sleep Modes
Intel
®
Media Processing Technology
— Multiply-Accumulate Coprocessor
High Performance External Bus
— 64- or 32-Bit Data Interface
— Optional ECC Protection
— Frequency up to 100 MHz
— Asynchronous to Processor Clock
Performance Monitoring Unit
— Two 32-Bit Event Counters
— One 32-Bit Clock Counter
— Monitors Occurrence and Duration
Events
Debug Unit
— Accessible through JTAG Port
— Hardware Breakpoints
— 256-Entry Trace Buffer
80200T can operate at an ambient
temperature range of -40C to +85C
January 2003
Reference Number: 273414-005
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
®
PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
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Intel may make changes to specifications and product descriptions at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
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Copyright© Intel Corporation, 2003
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*Other names and brands may be claimed as the property of others.
2
January 2003
Datasheet - Commercial and Extended Temperature (80200T)
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Contents
1.0
2.0
About this Document .......................................................................................................... 5
Functional Overview........................................................................................................... 5
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3.0
3.1
Superpipeline ........................................................................................................7
Branch Target Buffer (BTB)................................................................................... 8
Instruction Memory Management Unit (IMMU) ..................................................... 8
Data Memory Management Unit (DMMU)............................................................. 9
Instruction Cache (I-Cache) .................................................................................. 9
Data Cache (D-Cache)........................................................................................10
Mini-Data Cache..................................................................................................10
Fill Buffer (FB) and Pend Buffer (PB) ..................................................................11
Write Buffer (WB) ................................................................................................11
Multiply-Accumulate Coprocessor (CP0) ............................................................11
Clock and Power Management ...........................................................................12
Performance Monitoring Unit (PMU) ...................................................................12
Debug Unit ..........................................................................................................12
Extended Temperature (80200T) ........................................................................12
Package Introduction...........................................................................................13
3.1.1 Functional Signal Definitions ..................................................................13
3.1.1.1 Signal Pin Descriptions .............................................................13
3.1.2 241 Lead PBGA Package ......................................................................17
Package Thermal Specifications .........................................................................22
Package Thermal Resistance .............................................................................22
Absolute Maximum Ratings.................................................................................24
V
CCA
Pin Requirements ......................................................................................25
Targeted DC Specifications.................................................................................26
Targeted AC Specifications.................................................................................27
4.4.1 Clock Signal Timings..............................................................................27
4.4.2 Bus Signal Timings.................................................................................28
4.4.3 Boundary Scan Test Signal Timings ......................................................29
AC Timing Waveforms ........................................................................................30
Power Sequence .................................................................................................32
Reset Timing .......................................................................................................34
AC Test Conditions .............................................................................................34
Typical Power Dissipation ...................................................................................35
Package Information ........................................................................................................13
3.2
3.3
4.0
4.1
4.2
4.3
4.4
Electrical Specifications....................................................................................................24
4.5
4.6
4.7
4.8
4.9
Datasheet - Commercial and Extended Temperature (80200T)
January 2003
3
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Intel
®
80200 Processor Block Diagram ................................................................. 6
241-Lead PBGA Package ................................................................................... 17
Case Temperature with No Air Flow ................................................................... 23
Case Temperature at Nominal Power Dissipation .............................................. 23
V
CCA
Lowpass Filter............................................................................................ 25
CLK Waveform.................................................................................................... 30
MCLK Waveform................................................................................................. 30
T
OV
Output Delay Waveform .............................................................................. 31
Correct Power Sequence for V
CC
, V
CCP ............................................................................. 32
Another Correct Power Sequence for V
CC
, V
CCP ............................................................32
Incorrect Power Sequence for V
CC
, V
CCP........................................................................... 32
Preferred Power Sequence for VCC, VCCa ....................................................... 33
Correct Power Sequence for VCC, VCCa........................................................... 33
Pins’ State at Reset............................................................................................. 34
AC Test Load ...................................................................................................... 34
Typical Pin Power Dissipation............................................................................. 35
Typical Core Power Dissipation .......................................................................... 35
Tables
1
2
4
3
5
6
7
8
9
10
11
12
13
14
15
16
Related Documentation......................................................................................... 5
Pin Description Nomenclature............................................................................. 13
Signal Pin Description ......................................................................................... 14
Power Pins .......................................................................................................... 14
JTAG Pins ........................................................................................................... 16
241-Lead PBGA Pinout — Ballpad Number Order ............................................. 18
241-Lead PBGA Pinout — Signal Name Order .................................................. 20
Package Thermal Resistance — °C/Watt ........................................................... 22
Operating Conditions .......................................................................................... 24
Voltage Range Requirements for Intel
®
80200 Processor Product Options ....... 24
DC Characteristics .............................................................................................. 26
I
CC
Characteristics .............................................................................................. 26
Input Clock Timings............................................................................................. 27
Output Timings.................................................................................................... 28
Input Timings....................................................................................................... 28
Boundary Scan Test Signal Timings ................................................................... 29
4
January 2003
Datasheet - Commercial and Extended Temperature (80200T)
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture
About this Document
1.0
About this Document
This is the Advance Information data sheet for the Intel
®
80200 processor based on Intel
®
XScale
™
microarchitecture (ARM* architecture compliant). This data sheet contains a functional overview,
mechanical data (package signal locations and simulated thermal characteristics), targeted
electrical specifications (simulated), and bus functional waveforms. Detailed functional
descriptions other than parametric performance is published in the
Intel
®
80200 Processor based
on Intel
®
XScale
™
Microarchitecture Developer’s Manual.
Table 1.
Related Documentation
Document Title
Document #
273411
273415
273354
273410
273425
273416
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture Developer’s Manual
Intel
®
80200 Processor based on Intel
®
XScale
™
Microarchitecture Specification Update
Intel
®
80310 I/O Processor Chipset Design Guide
Intel
®
80312 I/O Companion Chip Developer’s Manual
Intel
®
80312 I/O Companion Chip Datasheet
Intel
®
80312 I/O Companion Chip Specification Update
2.0
Functional Overview
The Intel
®
80200 processor technology is compliant with the ARM* Version 5TE instruction set
architecture (ISA). The Intel
®
80200 processor is designed with Intel state-of-the-art 0.18 micron
production semiconductor process technology. This process technology, along with the
compactness of the ARM RISC ISA, enables the Intel
®
80200 processor to operate over a wide
speed/power range, producing industry-leading mW/MIPS performance.
•
7-8 stage Superpipeline promotes high speed, efficient core performance
•
128-entry Branch Target Buffer keeps pipeline filled with statistically correct branch choices
•
32-entry Instruction Memory Management Unit for logical-to-physical address translation,
access permissions, I-Cache attributes
•
32-entry Data Memory Management Unit for logical-to-physical address translation, access
permissions, D-Cache attributes
•
32 KB Instruction Cache can hold entire programs, preventing core stalls caused by multicycle
memory accesses
•
32 KB Data Cache reduces core stalls caused by multicycle memory accesses
•
2 KB Minidata Cache for frequently changing data streams avoids “thrashing” of the D-Cache
•
4-entry Fill and Pend Buffers promote core efficiency by allowing “hit-under- miss” operation
with Data Caches
•
Power Management Unit gives power savings via idle, and sleep modes
•
8-entry Write Buffer allows the core to continue execution while data is written to memory
•
Multiply-Accumulate Coprocessor can do two simultaneous 16-bit SIMD multiplies with
40-bit accumulation for efficient, high quality audio
Datasheet - Commercial and Extended Temperature (80200T)
January 2003
5