HD74AC164/HD74ACT164
Serial-In, Parallel-Out Shift Register
REJ03D0253–0200Z
(Previous ADE-205-373 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC164/HD74ACT164 is a high-speed 8-bit serial-in/parallel-out shift register. Serial data is entered through
a 2-input AND gate synchronous with the Low-to-High transition of the clock. The device features an asynchronous
Master Reset which clears the register, setting all outputs Low independent of the clock.
Features
•
Outputs Source/Sink 24 mA
•
HD74ACT164 has TTL-Compatible Inputs
•
Ordering Information
Part Name
HD74AC164P
HD74AC164FPEL
HD74AC164RPEL
HD74AC164TELL
Package Type
DIP-14 pin
SOP-14 pin (JEITA)
SOP-14 pin (JEDEC)
TSSOP-14 pin
Package Code Package Abbreviation Taping Abbreviation (Quantity)
DP-14, -14AV
FP-14DAV
FP-14DNV
TTP-14DV
P
FP
RP
T
—
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
A 1
B 2
Q
0
3
Q
1
4
Q
2
5
Q
3
6
GND 7
(Top view)
14 V
CC
13 Q
7
12 Q
6
11 Q
5
10 Q
4
9
MR
8 CP
Rev.2.00, Jul.16.2004, page 1 of 8
HD74AC164/HD74ACT164
Logic Symbol
A
B
CP
MR Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Pin Names
A, B
CP
MR
Q
0
to Q
7
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active Low)
Outputs
Functional Description
The HD74AC164/HD74ACT164 is an edge-triggered 8-bit shift register with serial data entry and an output from each
of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an
active High Enable for data entry through the other inputs. An unused input must be tied High.
Each Low-to-High transition on the Clock (CP) input shifts data one place to the right and enters into Q
0
the logical
AND of the two data inputs (A•B) that existed before the rising clock edge. A Low level on the Master Reset (MR)
input overrides all other inputs and clears the register asynchronously, forcing all Q outputs Low.
Mode Select Table
Inputs
Operating Mode
Reset (Clear)
Shift
MR
L
H
H
H
H
X
L
L
H
H
A
X
L
H
L
H
B
L
L
L
L
H
Q
0
Outputs
Q
1
to Q
7
L to L
q
0
to q
6
q
0
to q
6
q
0
to q
6
q
0
to q
6
H
L
X
q
n
:
:
:
:
High Voltage Level
Low Voltage Level
Immaterial
Lower case letters indicate the state of the referenced input or output one setup time prior to the Low-to-High
clock transition.
Logic Diagram
A
B
D
C
D
CP
MR
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
D
C
D
Q
D
C
D
Q
D
C
D
Q
D
C
D
Q
D
C
D
Q
D
C
D
Q
D
C
D
Q
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Rev.2.00, Jul.16.2004, page 2 of 8
HD74AC164/HD74ACT164
Absolute Maximum Ratings
Item
Supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or ground current per output pin
Storage temperature
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
, I
GND
Tstg
Ratings
–0.5 to 7
–20
20
–0.5 to Vcc+0.5
–50
50
–0.5 to Vcc+0.5
±50
±50
–65 to +150
Unit
V
mA
mA
V
mA
mA
V
mA
mA
°C
Condition
V
I
= –0.5V
V
I
= Vcc+0.5V
V
O
= –0.5V
V
O
= Vcc+0.5V
Recommended Operating Conditions: HD74AC164
Item
Supply voltage
Input and output voltage
Operating temperature
Input rise and fall time
(except Schmitt inputs)
V
IN
30% to 70% V
CC
Symbol
V
CC
V
I
, V
O
Ta
tr, tf
Ratings
2 to 6
0 to V
CC
–40 to +85
8
V
V
°C
ns/V
V
CC
= 3.0V
V
CC
= 4.5 V
V
CC
= 5.5 V
Unit
Condition
DC Characteristics: HD74AC164
Item
Sym-
bol
V
IH
Vcc
(V)
3.0
4.5
5.5
V
IL
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
V
OL
5.5
3.0
4.5
5.5
3.0
4.5
Input leakage
current
Dynamic output
current*
I
IN
I
OLD
I
OHD
5.5
5.5
5.5
5.5
min.
2.1
3.15
3.85
—
—
—
2.9
4.4
5.4
2.58
3.94
4.94
—
—
—
—
—
—
—
—
—
Ta = 25°C
°
typ.
1.5
2.25
2.75
1.50
2.25
2.75
2.99
4.49
5.49
—
—
—
0.002
0.001
0.001
—
—
—
—
—
—
max.
—
—
—
0.9
1.35
1.65
—
—
—
—
—
—
0.1
0.1
0.1
0.32
0.32
0.32
±0.1
—
—
Ta = –40 to
+85°C
°
min.
2.1
3.15
3.85
—
—
—
2.9
4.4
5.4
2.48
3.80
4.80
—
—
—
—
—
—
—
86
–75
—
max.
—
—
—
0.9
1.35
1.65
—
—
—
—
—
—
0.1
0.1
0.1
0.37
0.37
0.37
±1.0
—
—
80
µA
mA
mA
µA
V
V
OUT
= 0.1 V or V
CC
–0.1 V
Unit
Condition
Input Voltage
V
V
OUT
= 0.1 V or V
CC
–0.1 V
Output voltage
V
OH
V
IN
= V
IL
or V
IH
I
OUT
= –50
µA
V
IN
= V
IL
or V
IH
I
OH
= –12 mA
I
OH
= –24 mA
I
OH
= –24 mA
V
IN
= V
IL
or V
IH
I
OUT
= 50
µA
V
IN
= V
IL
or V
IH
I
OL
= 12 mA
I
OL
= 24 mA
I
OL
= 24 mA
V
IN
= V
CC
or GND
V
OLD
= 1.1 V
V
OHD
= 3.85 V
V
IN
= V
CC
or ground
Quiescent supply
5.5
—
—
8.0
I
CC
current
*Maximum
test duration 2.0 ms, one output loaded at a time.
Rev.2.00, Jul.16.2004, page 3 of 8
HD74AC164/HD74ACT164
Recommended Operating Conditions: HD74ACT164
Item
Supply voltage
Input and output voltage
Operating temperature
Input rise and fall time
(except Schmitt inputs)
V
IN
0.8 to 2.0 V
Symbol
V
CC
V
I
, V
O
Ta
tr, tf
Ratings
2 to 6
0 to V
CC
–40 to +85
8
V
V
°C
ns/V
V
CC
= 4.5V
V
CC
= 5.5V
Unit
Condition
DC Characteristics: HD74ACT164
Item
Sym-
bol
V
IH
V
IL
Output voltage
V
OH
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
V
OL
5.5
4.5
5.5
4.5
Input current
I
CC
/input current
Dynamic output
current*
Quiescent supply
current
I
IN
I
CCT
I
OLD
I
OHD
I
CC
5.5
5.5
5.5
5.5
5.5
5.5
min.
2.0
2.0
—
—
4.4
5.4
3.94
4.94
—
—
—
—
—
—
—
—
—
Ta = 25°C
°
typ.
1.5
1.5
1.5
1.5
4.49
5.49
—
—
0.001
0.001
—
—
—
0.6
—
—
—
max.
—
—
0.8
0.8
—
—
—
—
0.1
0.1
0.32
0.32
±0.1
—
—
—
8.0
Ta = –40 to
+85°C
°
min.
2.0
2.0
—
—
4.4
5.4
3.80
4.80
—
—
—
—
—
—
86
–75
—
max.
—
—
0.8
0.8
—
—
—
—
0.1
0.1
0.37
0.37
±1.0
1.5
—
—
80
µA
mA
mA
mA
µA
V
Unit
Condition
Input voltage
V
V
OUT
= 0.1 V or Vcc–0.1 V
V
OUT
= 0.1 V or Vcc–0.1 V
V
IN
= V
IL
or V
IH
I
OUT
= –50
µA
V
IN
= V
IL
V
IN
= V
IL
or V
IH
I
OUT
= 50
µA
V
IN
= V
IL
V
IN
= V
CC
or GND
V
IN
= V
CC
–2.1 V
V
OLD
= 1.1 V
V
OHD
= 3.85 V
V
IN
= V
CC
or ground
I
OL
= 24 mA
I
OL
= 24 mA
I
OH
= –24 mA
I
OH
= –24 mA
*Maximum
test duration 2.0 ms, one output loaded at a time.
AC Characteristics: HD74AC164
Ta = +25°C
C
L
= 50 pF
Item
Maximum clock
frequency
Propagation delay
CP to Q
n
Propagation delay
CP to Q
n
Propagation delay
Symbol
f
max
t
PLH
t
PHL
t
PHL
V
CC
(V)*
1
Min
3.3
125
5.0
3.3
5.0
3.3
5.0
3.3
150
1.0
1.0
1.0
1.0
1.0
1.0
Typ
—
—
8.5
6.5
8.5
6.5
9.5
7.5
Max
—
—
13.0
10.0
13.0
10.0
16.0
11.5
Ta = –40°C to +85°C
C
L
= 50 pF
Min
100
125
1.0
1.0
1.0
1.0
1.0
1.0
—
—
13.5
10.5
14.5
10.5
18.0
13.5
Max
MHz
ns
Unit
5.0
MR
to Q
n
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 4 of 8
HD74AC164/HD74ACT164
AC Operating Requirements: HD74AC164
Ta = +25°C
C
L
= 50 pF
Item
Setup time A or B to CP
Hold time CP to A or B
Pulse width CP or
MR
Recovery time
MR
or CP
Note:
Symbol V
CC
(V)*
1
Typ
t
su
3.3
3.0
t
h
t
w
t
rec
5.0
3.3
5.0
3.3
5.0
3.3
5.0
1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
2.0
–1.5
–1.5
2.0
2.0
0.0
0.0
Ta = –40°C
to +85°C
C
L
= 50 pF
Unit
ns
Guaranteed Minimum
5.5
6.0
4.0
0.0
0.0
5.5
4.5
2.0
2.0
4.5
0.0
0.0
7.0
5.0
2.0
2.0
AC Characteristics: HD74ACT164
Ta = +25°C
C
L
= 50 pF
Item
Symbol V
CC
(V)*
1
Maximum clock
f
max
5.0
frequency
Propagation delay
t
PLH
5.0
CP to Q
n
Propagation delay
t
PHL
5.0
CP to Q
n
Propagation delay
t
PHL
5.0
MR
to Q
n
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Min
100
1.0
1.0
1.0
Typ
—
9.0
9.0
9.5
Max
—
11.5
11.5
13.0
Ta = –40°C to +85°C
C
L
= 50 pF
Min
80
1.0
1.0
1.0
—
12.5
12.5
14.5
Max
MHz
ns
Unit
AC Operating Requirements: HD74AC164
Ta = –40°C
to +85°C
Ta = +25°C
C
L
= 50 pF
C
L
= 50 pF
Typ
Guaranteed Minimum
2.5
0.0
4.5
0.0
7.0
1.5
7.0
2.0
8.0
1.5
8.0
2.0
ns
Item
Setup time A or B to CP
Hold time CP to A or B
Pulse width CP or
MR
Recovery time
MR
or CP
Note:
Symbol V
CC
(V)*
1
t
su
t
h
t
w
t
rec
5.0
5.0
5.0
5.0
Unit
1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item
Input capacitance
Power dissipation capacitance
Symbol
C
IN
C
PD
4.5
20.0
Typ
pF
pF
Unit
V
CC
= 5.5 V
V
CC
= 5.0 V
Condition
Rev.2.00, Jul.16.2004, page 5 of 8
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