Low Voltage 2.5V/3.3V Differential ECL/
PECL/HSTL Fanout Buffer
The MC100ES6210 is a bipolar monolithic differential clock fanout buffer. Designed for
most demanding clock distribution systems, the MC100ES6210 supports various
applications that require to distribute precisely aligned differential clock signals. Using SiGe
technology and a fully differential architecture, the device offers very low clock skew outputs
and superior digital signal characteristics. Target applications for this clock driver is high
performance clock distribution in computing, networking and telecommunication systems.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Dual 1:5 differential clock distribution
30 ps maximum device skew
Fully differential architecture from input to all outputs
SiGe technology supports near-zero output skew
Supports DC to 3GHz operation of clock or data signals
ECL/PECL compatible differential clock outputs
ECL/PECL compatible differential clock inputs
Single 3.3V,
–
3.3V, 2.5V or
–
2.5V supply
Standard 32 lead LQFP and VFQFN packages
Industrial temperature range
Pin and function compatible to the MC100EP210
32-lead Pb-free Package Available
MC100ES6210
DATA SHEET
LOW VOLTAGE DUAL
1:5 DIFFERENTIAL PECL/ECL/HSTL
CLOCK FANOUT BUFFER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
Functional Description
The MC100ES6210 is designed for low skew clock distribution systems and supports
clock frequencies up to 3GHz. The device consists of two independent 1:5 clock fanout
buffers. The input signal of each fanout buffer is distributed to five identical, differential ECL/
PECL outputs. Both CLKA and CLKB inputs can be driven by ECL/PECL compatible
signals.
If V
BB
is connected to the CLKA or CLKB input and bypassed to GND by a 10nF
capacitor, the MC100ES6210 can be driven by single-ended ECL/PECL signals utilizing the
V
BB
bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential
output pair should be terminated, even if only one output is used. In the case where not all
ten outputs are used, the output pairs on the same package side as the parts being used on
that side should be terminated.
The MC100ES6210 can be operated from a single 3.3V or 2.5V supply. As most other
ECL compatible devices, the MC100ES6210 supports positive (PECL) and negative (ECL)
supplies. The is function and pin compatible to the MC100EP210.
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
K SUFFIX
32-LEAD VFQFN PACKAGE
Pb-FREE PACKAGE
ORDERING INFORMATION
Device
MC100ES6210FA
MC100ES6210FAR2
MC100ES6210AC
MC100ES6210ACR2
MC100ES6210KLF
Package
LQFP-32
LQFP-32
LQFP-32 (Pb-Free)
LQFP-32 (Pb-Free)
VFQFN-32 (Pb-Free)
MPC100ES6210 REVISION 5
MARCH 20, 2012
1
©2012 Integrated Device Technology, Inc.
MPC100ES6210 Data Sheet
LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER
QA4
QA3
QA3
QA4
QB0
QB0
QB1
18
V
CC
CLKA
CLKA
QA1
QA1
QA2
QA2
QA3
QA3
QA4
QA4
QB0
QB0
QB1
QB1
QB2
QB2
QB3
QB3
QB4
QB4
24
23
22
21
20
19
QB1
17
16
15
QA0
QA0
V
CC
QA2
QA2
QA1
QA1
QA0
QA0
V
CC
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
V
CC
QB2
QB2
QB3
QB3
QB4
QB4
V
CC
MC100ES6210
32 LQFP
14
13
12
11
10
9
V
CC
CLKB
CLKB
CLKA
CLKB
CLKB
N.C.
V
BB
Figure 1. MC100ES6210 Logic Diagram
Figure 2. 32-Lead LQFP Package Pinout
(Top View)
QA0
QA0
QA1
QA1
QA2
QA2
V
CC
32 31 30 29 28 27 26 25
V
CC
NC
CLKA
CLKA
V
BB
CLKB
CLKB
V
EE
1
2
3
4
5
6
7
8
9
V
CC
V
CC
24
23
22
QA3
QA3
QA4
QA4
QB0
QB0
QB1
QB1
MC100ES6210
32 VFQFN
21
20
19
18
17
10 11 12 13 14 15 16
QB2
QB4
QB4
QB3
QB3
QB2
V
CC
Figure 3. 32-Lead VFQFN Package Pinout
(Top View)
MPC100ES6210 REVISION 5 MARCH 20, 2012
2
CLKA
V
CC
©2012 Integrated Device Technology, Inc.
V
EE
V
BB
MPC100ES6210 Data Sheet
LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER
Table 1. Pin Configuration
Pin
CLKA, CLKA
CLKB, CLKB
QA[0-4], QA[0-4]
QB[0-4], QB[0-4]
V
EE(1)
V
CC
V
BB
Input
Input
Output
Output
Supply
Supply
Output
DC
I/O
Type
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
Function
Differential reference clock signal input (fanout buffer A)
Differential reference clock signal input (fanout buffer B)
Differential clock outputs (fanout buffer A)
Differential clock outputs (fanout buffer B)
Negative power supply
Positive power supply. All V
CC
pins must be connected to the positive
power supply for correct DC and AC operation.
Reference voltage output for single ended ECL or PECL operation
1. In ECL mode (negative power supply mode), V
EE
is either –3.3V or –2.5V and V
CC
is connected to GND (0 V). In PECL mode (positive power
supply mode), V
EE
is connected to GND (0V) and V
CC
is either +3.3V or +2.5V. In both modes, the input and output levels are referenced
to the most positive supply (V
CC
)
Table 2. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage temperature
–65
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.6
V
CC
0.3
V
CC
0.3
20
50
125
Unit
V
V
V
mA
mA
C
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
MPC100ES6210 REVISION 5
MARCH 20, 2012
3
©2012 Integrated Device Technology, Inc.
MPC100ES6210 Data Sheet
LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER
Table 3. General Specifications
Symbol
V
TT
MM
HBM
CDM
LU
C
IN
JA
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
ESD Protection (Charged Device Model)
Latch-Up Immunity
Input Capacitance
Thermal Resistance Junction to Ambient 32 LQFP
JESD 51-3, single layer test board
200
4.0
83.1
73.3
68.9
63.8
57.4
59.0
54.4
52.5
50.4
47.8
53.3
46.6
41.8
23.0
26.3
110
86.0
75.4
70.9
65.3
59.6
60.6
55.7
53.8
51.5
48.8
200
2000
Min
Typ
V
CC
– 2
(1)
Max
Unit
V
V
V
V
mA
pF
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C
Inputs
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
0 meters per second
1 meters per second
2.5 meters per second
MIL-SPEC 883E
Method 1012.1
Condition
JESD 51-6, 2S2P multilayer test board
Thermal Resistance Junction to Ambient 32 VFQFN
JC
T
J
Thermal Resistance Junction to Case 32 LQFP
Operating Junction Temperature
(2)
(continuous operation)
MTBF = 9.1 years
1. Output termination voltage V
TT
= 0V for V
CC
= 2.5V operation is supported but the power consumption of the device will increase.
2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are
specified up to 110C junction temperature allowing the MC100ES6210 to be used in applications requiring industrial temperature range. It
is recommended that users of the MC100ES6210 employ thermal modeling analysis to assist in applying the junction temperature
specifications to their particular application.
Table 4. PECL DC Characteristics
(V
CC
= 2.5V
5% or V
CC
= 3.3V
5%, V
EE
= GND, T
J
= 0C to +110C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL differential signals)
V
PP
V
CMR
I
IN
Differential Input Voltage
(1)
Differential Cross Point Voltage
(2)
Input Current
(1)
0.1
1.0
1.3
V
CC
– 0.3
100
V
V
A
Differential operation
Differential operation
V
IN
= V
IL
or V
IN
= V
IH
I
OH
= –30 mA
(3)
I
OL
= –5 mA
(3)
PECL Clock Outputs (QA0-4, QA0-4, QB0-4, QB0-4)
V
OH
V
OL
Output High Voltage
Output Low Voltage
V
CC
= 3.3V
5%
V
CC
= 2.5V
5%
V
CC
–1.2
V
CC
–1.9
V
CC
–1.9
V
CC
–1.005
V
CC
–1.705
V
CC
–1.705
V
CC
–0.7
V
CC
–1.5
V
CC
–1.3
V
V
Supply Current and V
BB
I
EE
V
BB
Maximum Quiescent Supply Current
without Output Termination Current
Output Reference Voltage
V
CC
–1.38
60
V
CC
–1.26
100
V
CC
–1.14
mA
V
V
EE
pin
I
BB
= 0.2 mA
1. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
2. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
3. Equivalent to a termination of 50
to V
TT
.
MPC100ES6210 REVISION 5 MARCH 20, 2012
4
©2012 Integrated Device Technology, Inc.
MPC100ES6210 Data Sheet
LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER
Table 5. ECL DC Characteristics
(V
EE
=
–
2.5V
5% or V
EE
=
–
3.3V
5%, V
CC
= GND, T
J
= 0C to +110C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (ECL differential signals)
V
PP
V
CMR
I
IN
Differential Input Voltage
(1)
Differential Cross Point Voltage
(2)
Input Current
(1)
0.1
V
EE
+ 1.0
1.3
–0.3
100
V
V
A
Differential operation
Differential operation
V
IN
= V
IL
or V
IN
= V
IH
I
OH
= –30 mA
(3)
I
OL
= –5 mA
(3)
ECL Clock Outputs (QA0–4, QA0–4, QB0–4, QB0–4)
V
OH
V
OL
Output High Voltage
Output Low Voltage
V
CC
= 3.3V
5%
V
CC
= 2.5V
5%
–1.2
–1.9
–1.9
–1.005
–1.705
–1.705
–0.7
–1.5
–1.3
V
V
Supply Current and V
BB
I
EE
V
BB
Maximum Quiescent Supply Current
without Output Termination Current
Output Reference Voltage
–1.38
60
–1.26
100
–1.14
mA
V
V
EE
pin
I
BB
= 0.2 mA
1. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
2. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC)
range and the input swing lies within the V
PP
(DC) specification.
3. Equivalent to a termination of 50
to V
TT
.
MPC100ES6210 REVISION 5
MARCH 20, 2012
5
©2012 Integrated Device Technology, Inc.
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