HD49323AF-01
CDS/AGC & 10-bit A/D Converter
ADE-207-262A (Z)
2nd Edition
Apr. 1999
Description
The HD49323AF-01 is a CMOS IC that provides CCD-AGC analog processing (CDS/AGC) suitable for
CCD camera digital signal processing systems together with a 10-bit A/D converter in a single chip.
Functions
•
•
•
•
•
•
•
•
•
Correlated Double Sampling
AGC
Sample hold
Offset compensation
Serial interface control
10-bit ADC
3 V single operation (2.7 V to 3.6 V)
Power dissipation: 198 mW (Typ)
Maximum frequency: 20 MHz (Min)
Features
•
Good suppression of CCD output low-frequency noise is achieved through the use of S/H type
correlated double sampling.
•
A high S/N ratio is achieved through the use of a AGC type amplifier, and high sensitivity is provided
by a wide cover range.
•
An auto offset circuit provides compensation of output DC offset voltage fluctuations due to variations
in AGC amplifier gain.
•
AGC, standby mode, offset control, etc., is possible via a serial interface.
•
High precision is provided by a 10-bit-resolution A/D converter.
•
Version of Hitachi’s previous-generation HD49322BF with improved functions and performance,
including in particular an approximately 3.0 dB improvement in S/N.
HD49323AF-01
Pin Arrangement
NC
BIAS
VRT
VRM
VRB
AV
DD
AV
SS
TESTC
TESTY
CDSIN
AV
DD
AV
SS
AV
SS
AV
DD
NC
NC
AV
DD
AV
SS
CS
SCK
SDATA
DV
DD
DV
SS
DV
SS
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
39
22
40
21
41
20
42
19
43
18
44
17
45
16
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
PBLK
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
NC
(Top view)
2
VRM2
CLP
NC
AV
DD
AV
SS
SPSIG
SPBLK
OBP
ADCLK
DV
DD
DV
SS
OE
HD49323AF-01
Pin Description
Pin No.
1
2
3 to 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Symbol
PBLK
D0
D1 to D8
D9
NC
OE
DV
SS
DV
DD
ADCLK
OBP
SPBLK
SPSIG
AV
SS
AV
DD
NC
CLP
VRM2
AV
SS
AV
DD
CDSIN
TESTY
TESTC
AV
SS
AV
DD
VRB
VRM
VRT
Description
Pre-blanking pin
Digital output (LSB)
Digital output
Digital output (MSB)
No connection pin
Digital output enable control pin
Digital ground (0 V)
Digital power supply (3 V)
Connect off-chip in common with AV
DD
.
ADC conversion clock input pin
Optical black pulse input pin
Black level sampling clock input pin
Signal level sampling clock input pin
Analog ground (0 V)
Analog power supply (3 V)
Connect off-chip in common with DV
DD
.
No connection pin
Clamp voltage pin
Connect a 0.22
µF
or more capacitor between CLP and AV
SS
.
Reference voltage pin (for CCD offset cancel)
Analog ground (0 V)
Analog power supply (3 V)
Connect off-chip in common with DV
DD
.
CDS input pin
Test input pin-Y
Test input pin-C
Analog ground (0 V)
Analog power supply (3 V)
Connect off-chip in common with DV
DD
.
Reference voltage pin 3
Connect a 0.1
µF
ceramic capacitor between VRB and AV
SS
.
Reference voltage pin 2
Connect a 0.1
µF
ceramic capacitor between VRM and AV
SS
.
Reference voltage pin 1
Connect a 0.1
µF
ceramic capacitor between VRT and AV
SS
.
I/O
I
O
O
O
—
I
—
—
I
I
I
I
—
—
—
—
—
—
—
I
I
I
—
—
—
—
—
Analog(A) or
Digital(D)
D
D
D
D
—
D
D
D
D
D
D
D
A
A
—
A
A
A
A
A
A
A
A
A
A
A
A
3
HD49323AF-01
Pin Description
(cont)
Pin No.
35
36
37
38
39, 40
41
42
43
44
45
46
47, 48
Symbol
BIAS
NC
AV
SS
AV
DD
NC
AV
DD
AV
SS
CS
SCK
SDATA
DV
DD
DV
SS
Description
Internal bias pin
Connect a 24 kΩ resistor between BIAS and AV
SS
.
No connection pin
Analog ground (0 V)
Analog power supply (3 V)
Connect off-chip in common with DV
DD
.
No connection pin
Analog power supply (3 V)
Connect off-chip in common with DV
DD
.
Analog ground (0 V)
Serial interface control input pin
Serial clock input pin
Serial data input pin
Digital power supply (3 V)
Connect off-chip in common with AV
DD
.
Digital ground (0 V)
I/O
—
—
—
—
—
—
—
I
I
I
—
—
Analog(A) or
Digital(D)
A
—
A
A
—
A
A
D
D
D
D
D
4
HD49323AF-01
Input/Output Equivalent Circuit
Pin Name
Digital output
D0 to D9
DIN
STBY
or
OE
Digital input
ADCLK
OBP
SPBLK
SPSIG
CS
SCK
SDATA
PBLK
OE
CDSIN
Digital
input
*1
70kΩ
(Typ)
Digital
output
Equivalent Circuit
DV
DD
Analog input
Connected to
VRM internally
CDSIN
Reference voltage input
VRT
VRM
VRB
VRM2
+
−
VRT
VRM VRM2 VRB
+
−
Clamp
CLP
AV
DD
Connected to
VRM internally
CLP
Internal bias
BIAS
BIAS
AV
DD
Note:
1. Applies to
OE
and PBLK.
5