CA82C37A
PROGRAMMABLE DMA CONTROLLER
• Pin and functional compatibility with the
industry standard 8237/8237A
• Fully static, high speed - 10, 8 and 5 MHz
versions available
• Low power CMOS implementation
• TTL input/output compatibility
• Compatible with 8080/85, 8086/88, 80286/386 and
68000
µP
families
• Fully static
• Four independent maskable DMA channels with
autoinitialize capability
• Memory-to-memory transfer
• Fixed or rotating DMA request priority
• Independent polarity control for DREQ and
DACK signals
• Address increment or decrement selection
• Cascadable to any number of channels
The CA82C37A is a high performance, programmable
Direct Memory Access (DMA) controller offering pin-for-
pin functional compatibility with industry standard
8237/8237A. It features four channels, each independently
programmable, and is cascadable to any number of channels.
Each channel can be programmed to auto-initialize
following DMA termination.
In addition, the CA82C37A supports memory-to-memory
transfer capability and memory block initialization, as well
as a programmable transfer mode.
The CA82C37A is designed to improve system performance
by allowing external devices to transfer data directly from
the system memory. High speed and very low power
consumption make it an ideal component for aerospace and
defence applications. The low power consumption also
makes it an attractive addition in portable systems, or
systems with low power standby modes.
2
2.2
CA82C37A
READY
MEMW
IOR
IOW
MEMR
MEMW
NC
READY
HLDA
ADSTB
AEN
HRQ
CS
CLK
RESET
DACK 2
DACK 3
DREQ 3
DREQ 2
DREQ 1
DREQ 0
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A6
A5
A4
EOP
A3
A2
A1
A0
V
DD
DB 0
DB 1
DB 2
DB 3
DB 4
DACK 0
DACK 1
DB 5
DB 6
DB 7
6
5
4
3
2
1
44
43
42
41
NC
NC
HLDA
ADSTB
AEN
HRQ
CS
CLK
RESET
DACK2
NC
40
EOP
IOW
NC
IOR
A7
A6
A5
A4
A7
MEMR
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
39
38
37
A3
A2
A1
A0
VDD
DB0
DB1
DB2
DB3
DB4
NC
DACK3
DACK1
DREQ3
DREQ2
DREQ1
DREQ0
Figure 2-1: PDIP Pin Configurations
Figure 2-2: PLCC Pin Configurations
Tundra Semiconductor Corporation
DACK0
VSS
DB7
DB6
DB5
CA82C37A
CA82C37A
44 - LEAD PLCC
36
35
34
33
32
31
30
29
2-17
CA82C37A
Tundra Semiconductor Corporation
DECREMENTOR
TERMINAL
COUNT
ADSTB
AEN
CS
CLOCK
EOP
IOR
IOW
MEMR
MEMW
READY
RESET
TEMPORARY WORD
COUNT REGISTER
(16)
INCREMENTOR /
DECREMENTOR
TEMPORARY
ADDRESS REGISTER
(16)
OUTPUT
BUFFER
A
4
A
7
-
I/O
BUFFER
BASE
WORD
COUNT
REGISTER
(4 X 16)
CURRENT
WORD
COUNT
REGISTER
(4 X 16)
-
A
8
A
15
A
0
A
3
-
TIMING
AND
CONTROL
CIRCUIT
BASE
CURRENT
ADDRESS ADDRESS
REGISTER REGISTER
(4 X 16)
(4 X 16)
D
0
D
1
-
COMMAND
CONTROL
INTERNAL DATA BUS
I/O
BUFFER
-
DB
0
DB
7
MODE
REGISTER
(4 X 6)
HLDA
HRQ
DREQ
0-3
PRIORITY
ENCODER
AND
ROTATING
PRIORITY
LOGIC
COMMAND
REGISTER
(8)
MASK
REGISTER
(4)
REQUEST
REGISTER
(4)
STATUS
REGISTER
(8)
TEMPORARY
REGISTER
(8)
DACK
0-3
Figure 2-3: CA82C37A Block Diagram
2-18
Tundra Semiconductor Corporation
Tundra Semiconductor Corporation
CA82C37A
Table 2-1: Pin Descriptions
Pins
Symbol
PLCC
A
0-3
36-39
PDIP
32-35
I/O
Low Address Bus:
Bi-directional, 3-state signals. The 4 least significant address lines. Idle
Cycle (Inputs). Addresses the CA82C37A control register to be loaded or read. Active Cycle
(Outputs). Lower 4 bits of the transfer address.
High Address Bus:
3-state output signals. The 4 most significant address lines representing
the upper 4 bits of the transfer address. Enabled during DMA service only.
Address Strobe:
Active HIGH output signal to control latching of the upper address byte.
Drives the strobe input of external transparent octal latches. During block operations,
ADSTB is activated only if the upper address byte needs updating, eliminating S1 states and
accelerating operation.
Address Enable:
Active HIGH output signal to enable the 8-bit latch containing the higher
order address byte onto the system address bus. During DMA transfers, it can disable other
system bus drivers.
Clock Input:
Generates timing signals to control internal operations and data transfer rate.
Input can be driven from DC to maximum frequency. CLK may be stopped in Active or Idle
Cycle for standby operation.
Chip Select:
Active LOW input signal to select the CA82C37A as an I/O device (Idle Cycle)
for CPU communication on the data bus.
DMA Acknowledge:
Individual channel active LOW (RESET) or HIGH (programmable)
output lines. Informs a peripheral that the requested DMA transfer has been granted.
Data Bus:
Bi-directional tri-state data lines connected to the system data bus. Idle Cycle.
During I/O Read (Program condition), outputs are enabled and contents of CA82C37A
internal registers are read by the CPU. In I/O Write, outputs are disabled and data from the
data bus are written into the registers. Active Cycle. The upper byte of the transfer address is
output to the data bus during DMA I/O device to-memory transfers. In memory-to-memory
transfers, data is read into the CA82C37A Temporary Register from data bus inputs during
the read-from-memory transfer, and written to the new memory location by data bus outputs
during the write-to-memory transfer.
DMA Request:
Asynchronous DMA service request input lines from I/O devices. DMA
service is requested by activation of the channel from a specific device. DREQ must be
maintained until DACK (service acknowledge) is activated. I/O Device Priority. Order of
service is programmable.Priority may be Fixed (descending order from Channel 0) or
Rotating (Most recent channel served gets the lowest priority).
Type
Name and Function
A
4-7
41-44
37-40
O
ADSTB
10
8
O
AEN
11
9
O
CLK
14
12
I
CS
13
28, 27,
16, 18
11
14, 15,
24, 25
I
O
DACK
0-3
DB
0-7
34-30
26-24
21-23
26-30
I/O
DREQ
0-3
19, 20,
21, 22
16, 17,
18, 19
I
Tundra Semiconductor Corporation
2-19
CA82C37A
Table 2-1: Pin Descriptions
Cont'd
Pins
Symbol
PLCC
PDIP
Type
Tundra Semiconductor Corporation
Name and Function
End of Process:
Active LOW bi-directional 3-state signal. The CA82C37A terminates DMA
service when
EOP
is activated. Internal
EOP
(Output).
EOP
is activated when the word count
for any channel turns over from 0000(H) to FFFF(H) and a TC pulse is generated. In
memory-to-memory transfers, service is terminated when TC for channel 1 occurs. External
EOP
(Input). An external
EOP
signal pulling
EOP
low terminates active DMA service. An
EOP
signal also resets the DMA request. If auto-initialize is enabled, the base registers are
written to the current registers of the channel. If the channel is not programmed for
auto-initialize, the mask bit (Mask Register) and TC bit (Status Register) are set for the
currently active channel. The mask bit is not changed if the channel is set for autoinitialize.
Since
EOP
is driven by an open drain transistor on-chip, it should be maintained HIGH with
a pull-up resistor in order to avoid erroneous
EOP
inputs.
Hold Acknowledge:
Active HIGH input signal to the CPU following an HRQ. Notifies the
CA82C37A that the CPU has released control of the system buses.
Hold Request:
Active HIGH out put signal to the CPU. Requests control of the system
buses. HRQ is issued following a request for DMA service (DREQ) from a peripheral, and is
acknowledged by the HLDA signal.
I/O Read:
Active LOW bi-directional, 3-state signal. Idle Cycle. CPU input control signal
for reading the Control Registers. Active Cycle. Output control signal to read data from a
peripheral device during a DMA cycle.
I/O Write:
Active LOW bi-directional, 3-state signal. Idle Cycle. CPU input control signal
for loading information into the CA82C37A. Active Cycle. Output control signal to load
data to a peripheral device during a DMA cycle.
Memory Read:
Active LOW 3-state output signal. CA82C37A reads data from a selected
memory address during a DMA Read or Memory-to-Memory transfer.
Memory Write:
Active LOW 3-state output signal. CA82C37A writes data to a selected
memory address during a DMA Write or Memory-to-Memory transfer.
Ready:
A LOW Ready signal extends the Memory Read and Write pulse widths from the
CA82C37A to accommodate slow I/O peripherals or memories. Transitions must not be
made during the specified setup/hold time.
Reset:
Active HIGH asynchronous input signal. Clears the Command, Status, Request and
Temporary Registers, the Mode Register Counter and the First/Last Flip-Flop. The Mask
Register is set to ignore DMA requests. The CA82C37A is in Idle Cycle following Reset.
Power:
5 V
±
10% DC Supply.
Ground:
0 V
EOP
40
36
I/O
HLDA
9
7
I
HRQ
12
10
O
IOR
2
2
I/O
IOW
2
2
I/O
MEMR
3
4
3
4
O
O
MEMW
READY
6
6
I
RESET
V
DD
V
SS
15
35
23
13
31
20
I
-
-
2-20
Tundra Semiconductor Corporation
Tundra Semiconductor Corporation
CA82C37A
FUNCTIONAL DESCRIPTION
The CA82C37A DMA controller is a state-driven address and
control signal generator designed to accelerate data transfer in
systems by moving data from an I/O device to memory, or a
block memory to an I/O device. Data transfers are direct,
rather than being stored enroute in a temporary register.
The CA82C37A also mediates memory-to-memory block
transfers and will move data from a single location to a
memory block. Temporary storage of data is required, but the
transfer rate is significantly faster than CPU processes. The
device provides operating modes to carry out both single byte
and block transfers of data. An operational flowchart of the
CA82C37A is shown in Figure 2-4.
The organization of the CA82C37A is shown in the block
diagram. It is composed of three logic blocks, a series of
internal registers and a counter section. The logic blocks
include the Timing Control, Command Control and Priority
Encoder circuits.
The Timing Control block generates internal timing signals
from the clock input and produces external control signals.
Command Control decodes incoming instructions from the
CPU, and the Priority Encoder block regulates DMA channel
priority.
The internal registers hold internal states and instructions
from the CPU. Addresses and word counts are computed in
the counter section.
Tundra Semiconductor Corporation
2-21
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