Freescale Semiconductor, Inc.
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Advance Information
MC33143
Dual High-Side Switch
The MC33143 is a dual high–side switch designed for solenoid control in
harsh automotive applications, but is well suited for other environments. The
device can also be used to control small motors and relays as well as
solenoids. The MC33143 incorporates SMARTMOS™ technology, with
CMOS logic, bipolar/MOS analog circuitry, and DMOS power outputs. An
internal charge pump is incorporated for efficient gate enhancement of the
internal high–side power output devices. The outputs are designed to
provide current to low impedance solenoids. The MC33143 provides
individual output fault status reporting along with internal Overcurrent and
Over Temperature protection. The device also has Overvoltage protection,
with automatic recovery, which “globally” disables both outputs for the
duration of an Overvoltage condition. Each output has individual Overcurrent
and Over Temperature shutdown with automatic retry recovery. Outputs are
enabled with a CMOS logic high signal applied to an input to providing true
logic control. The outputs, when turned on, provide full supply (battery)
voltage across the solenoid coil.
The MC33143 is packaged in an economical 24 pin surface mount power
package and specified over an operating voltage of 5.5 V
≤
VPwr < 26 V for
–40°C
≤
TA
≤
125°C.
•
Designed to Operate Over Wide Supply Voltages of 5.5 V to 26 V
DUAL HIGH–SIDE
SWITCH
SEMICONDUCTOR
TECHNICAL DATA
Freescale Semiconductor, Inc...
24
1
•
•
•
•
•
•
•
•
•
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Dual High–Side Outputs Clamped to –10 V for Driving Inductive Loads
Internal Charge Pump for Enhanced Gate Drive
Interfaces Directly to a Microcontroller with Parallel Input Control
Outputs Current Limited to 3.0 A to 6.0 A for Driving Incandescent Loads
Chip Enable “Sleep Mode” for Power Conservation
Individual Output Status Reporting
Fault Interrupt Output for System Interrupt Use
Output ON or OFF Open Load Detection
Overvoltage Detection and Shutdown
Output Over Temperature Detection and Shutdown with Automatic Retry
Sustained Current Limit or Immediate Overcurrent Shutdown Output Modes
Output Short to Ground Detection and Shutdown with Automatic Retry
Output Short to VPwr Detection
DW SUFFIX
PLASTIC PACKAGE
CASE 751E
(SOP (16+4+4)L)
PIN CONNECTIONS
IN1
CEN
STAT1
VPwr
Gnd
Gnd
Gnd
1
2
3
4
5
6
7
8
9
24 OUT1
23 INT
22 N/C
21 VPwr
20 Gnd
19 Gnd
18 Gnd
17 Gnd
16 VPwr
15 GTST
14 SFPD
13 OUT2
(Top View)
SMARTMOS is a trademark of Motorola, Inc.
Simplified Application
VDD
SFPD (14)
VDD (11)
V Pwr (16)
GTST (15)
+VPwr
Battery
Gnd
VPwr
STAT2 10
VDD 11
IN2 12
VDD P0
P1
P2
MCU
P3
P4
IRQ
NOTE:
CEN (2)
IN1 (1)
IN2 (12)
STAT1 (13)
STAT2 (10)
INT (23)
OUT1 (24)
OUT2 (13)
MC33143
Gnd (Note)
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
SOP–24L
Rev 0
Pins 5, 6, 7, 8, 17, 18, 19 and 20 provide electrical ground and heatsinking.
This device contains 889 active transistors.
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
DEVICE DATA
MOTOROLA ANALOG IC
MC33143DW TA = – 40° to +125°C
©
Motorola, Inc. 1996
For More Information On This Product,
Go to: www.freescale.com
1
MC33143
Freescale Semiconductor, Inc.
Figure 1. Simplified Internal Block Diagram
VPwr (9, 16)
Overvoltage
Shutdown
SFPD (14)
Voltage
Regulator
Current
Limit
Gate
Control
OFF/ON
Open Load
Detect
Bias
Charge
Pump
OFF/ON
Open Load
Detect
Gate
Control
4.0 ms
Retry Timer
Fault Detection
D
ON/OFF Open Load
D
ON/OFF VPwr Short
D
On Ground Short
D
Over Temperature
D
VPwr Overvoltage
–10 V
15 V
OUT2 (13)
STAT2 (10)
Fault Detection
D
ON/OFF Open Load
D
ON/OFF VPwr Short
D
On Ground Short
D
Over Temperature
D
VPwr Overvoltage
Current
Limit
Over
Temperature
Shutdown
–10 V
15 V
OUT1 (24)
STAT1 (3)
Over
Temperature
Shutdown
55 V
IN1 (1)
VDD (11)
GTST (15)
CEN (2)
55 V
INT (23)
Freescale Semiconductor, Inc...
IN2 (12)
Gnd (5) (See Note)
NOTE:
Pins 5, 6, 7, 8, 17, 18, 19 and 20 should all be grounded so as to provide electrical as well as thermal heatsinking of the device.
MAXIMUM RATINGS
(All voltages are with respect to ground, unless otherwise noted.)
Rating
Power Supply Voltage
Steady State Continuous Operation
Negative Transient (Note 1)
Positive Load Dump Transient (Note 2)
Logic Supply Voltage Range
Logic Supply Current
Symbol
VPwr
Value
26
–1.5
60
Unit
V
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Á
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Á
ÁÁÁ Á Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á Á
VDD
IDD
Vin
–0.3 to 7.0
5.0
V
mA
V
V
Input Voltage (Note 3)
–0.3 to 7.0
Output Clamp Voltage
IO = –20 mA
IO = –200 mA
VClamp
–3.0 to –20
–5.5 to –20
Output Current Limit (Note 4)
IO(Lim)
–3.0 to –6.0
300
100
A
Output Clamp Energy (IO = –1.0 A)
TJ = 25°C
TJ = 125°C
ESD (Minimum)
Human Body Model (Note 5)
Machine Model (Note 6)
EClamp
mJ
V
NOTES:
1. Negative transient survival capability
for 100 ms time duration.
2. Positive transient survival capability
with typical automotive load dump
condition; 400 ms time constant
decay.
3. All input pins (IN1–2, CEN and
SFPD).
4. Each output has independent
current limiting.
5. Performed in accordance to HBM;
CZap = 100 pF, RZap = 1500
Ω.
6. Performed in accordance to MM;
CZap = 100 pF, RZap = 0
Ω.
7. Derate Power Dissipation 33 mW/°C
for temperatures above 25°C.
8. Ambient temperature is given as a
practical reference; Maximum
junction temperature is the limiting
factor.
9. ESD data available upon request.
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Á
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Power Dissipation (TA = 25°C) (Note 7)
Operating Temperature (Note 8)
PD
TA
TJ
4.2
W
–40 to +125
–40 to +150
–55 to +150
270
15
30
°C
°C
°C
°C
Operating Junction Temperature
Storage Temperature
Tstg
Soldering Temperature (for 10 Seconds)
Thermal Resistance
Junction–to–Lead
Junction–to–Ambient
Tsolder
R
θJL
R
θJA
°C/W
HBM
MM
2000
200
2
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA ANALOG IC DEVICE DATA
MC33143
Freescale Semiconductor, Inc.
DC ELECTRICAL CHARACTERISTICS
(Characteristics noted under conditions 9.0 V
≤
VPwr
≤
17 V, 4.5 V
≤
VDD 5.5 V,
–40°C
≤
TL
≤
125°C, unless otherwise noted, typical values represent approximate mean at TL = 25°C.)
Characteristic
POWER INPUT
Symbol
Min
Typ
Max
Unit
Freescale Semiconductor, Inc...
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Á Á Á Á Á
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Á
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Supply Voltage Range (Operational)
VPwr
9.0
–
17
V
Supply Current (Note 1)
Both Outputs ON
(CEN = IN1 = IN2 = 0.7 x VDD, IO1 = IO2 = –1.0 A)
Standby (CEN = 0.7 x VDD, IN1 = IN2 = 0.3 x VDD, RL = 12
Ω)
“Sleep State” (CEN = IN1 = IN2 = 0.3 x VDD, RL = 12
Ω)
Logic Supply Voltage Range
IPwr
IPwr(sby)
IPwr(sleep)
VDD
IDD
0.1
–
–
4.5
–
4.2
3.9
0.2
–
7.0
7.0
300
5.5
5.0
38
mA
mA
µA
V
Logic Supply Current
Both Outputs ON (IN1 = IN2 = 0.7 x VDD, IO1 = IO2 = –1.0 A)
Overvoltage Shutdown (Note 2)
Overvoltage Shutdown Hysteresis
0.43
33.2
0.5
mA
V
V
VPwr(ovsd)
VPwr(hys)
30
0.3
1.5
NOTES:
1. Supply current when both outputs are ON and during standby are measured in the Ground pin while during “sleep state” is measured in the VPwr pin
.
2. Overvoltage Shutdown causes enabled outputs to be forced OFF; Overvoltage fault is immediately reported.
DC ELECTRICAL CHARACTERISTICS
(Characteristics noted under conditions 9.0 V
≤
VPwr
≤
17 V, 4.5 V
≤
VDD 5.5 V,
–40°C
≤
TL
≤
125°C, unless otherwise noted, typical values represent approximate mean at TL = 25°C.)
Characteristic
POWER OUTPUT
Symbol
Min
Typ
Max
Unit
Ω
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Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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Á Á Á Á Á
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Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á Á Á Á
Drain–to–Source ON Resistance (Note 1)
(TJ = 25°C, CEN = IN1 = IN2 = 0.7 x VDD)
IO = –0.5 A. VPwr = 5.5 V
IO = –1.0 A. VPwr = 14 V
IO = –2.0 A. VPwr = 24 V
RDS(on)
–
–
–
0.2
0.14
0.14
0.5
0.2
0.2
Drain–to–Source ON Resistance (Note 1)
(TJ = 125°C, CEN = IN1 = IN2 = 0.7 x VDD)
IO = –0.5 A. VPwr = 5.5 V
IO = –1.0 A. VPwr = 14 V
IO = –2.0 A. VPwr = 24 V
RDS(on)
Ω
–
–
–
–
–
–
1.0
0.38
0.38
–6.0
Output Self–Limiting Current (Note 2)
(CEN = IN1 = IN2 = SFPD = 0.7 x VDD, RL = 0
Ω)
Output OFF Leakage Current
(CEN = 0.7 x VDD, IN1 = IN2 = 0.3 x VDD)
Output OFF Open Load Sense Current
(CEN = 0.7 x VDD, IN1 = IN2 = 0.3 x VDD)
IO(Lim)
–3.0
–5.0
–5.0
–4.1
–45
–45
A
IO(Lkg)
–150
–150
µA
µA
IO(Sense)
IO(On)
Output ON Open Load Detection Current (Note 3)
(CEN = IN1 = IN2 = 0.7 x VDD)
TL = –40°C
TL = 125°C
Output Clamp Voltage (Note 4)
(CEN = 0.7 x VDD, IN1 = IN2 = 0.3 x VDD)
IO = –20 mA
IO = –200 mA
mA
–2.0
–2.0
–145
–181
–200
–200
VClamp
V
–9.0
–9.0
155
–
–13.2
–13.5
–
–
–20
–20
185
15
Over Temperature Shutdown Range (Note 5)
(CEN = IN1 = IN2 = SFPD = 0.7 x VDD)
TLim
°C
°C
Over Temperature Shutdown Hysteresis (Note 6)
TLim(hys)
NOTES:
1. RDS(on) applies to OUT1, OUT2 and is independent of output current.
2. Applies to each output; each output has independent self–limiting source current feature; Over Current and Short–to–Ground defined as condition
when output source current exceeds IO(Lim); Device ignores Over Current and Short–to–Ground faults from 0 to tss.
3. Applies to each output; tested for by ramping IO from 0 until STAT
≤
0.7 x VDD; defined as the condition when IO is outside of IO(on) current window.
4. Applies to each output; each output has independent dynamic output voltage clamping feature.
5. Applies to each output; each output has independent thermal shutdown; parameter is measured by ramping temperature until enabled output is
disabled; parameter is established by design but is not production tested; thermal fault is immediately reported.
6. Parameter is established by design but is not production tested.
MOTOROLA ANALOG IC DEVICE DATA
For More Information On This Product,
3
Go to: www.freescale.com
MC33143
Freescale Semiconductor, Inc.
DC ELECTRICAL CHARACTERISTICS
(Characteristics noted under conditions 9.0 V
≤
VPwr
≤
17 V, 4.5 V
≤
VDD 5.5 V,
–40°C
≤
TL
≤
125°C, unless otherwise noted, typical values represent approximate mean at TL = 25°C.)
Characteristic
CONTROL INTERFACE
Symbol
Min
Typ
Max
Unit
Freescale Semiconductor, Inc...
ÁÁÁ Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á Á Á Á Á
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Á
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Input Control
Logic High (IO = –0.1 A) (Note 1)
Logic Low (IO = 0) (Note 2)
VDD
VIH
VIL
0.7
–
50
20
0.56
0.52
250
44
–
0.3
Input Logic Voltage Hysteresis (VIH – VIL)
Vhys
500
100
0.3
–
mV
µA
Input Pull–Down Current (0.3 x VDD
≤
Vin < 0.7 x VDD) (Note 3)
Chip–Enable Threshold
Logic Low (Note 4)
Logic High (Note 5)
Iin(pd)
VDD
Chip–Enable Hysteresis (VCEN(IH) – VCEN(IL))
Status Low Voltage (Iin = 600
µA)
(Note 6)
Status Pull–Up Current (Note 7)
Interrupt (Note 8)
Logic High
Logic Low
VCEN(IL)
VCEN(IH)
VCEN(hys)
ICEN(pu)
–
0.7
50
0.5
0.5
150
500
–40
0.2
mV
µA
Chip–Enable Pull–Up Current (CEN = 0.7 x VDD)
–2.0
–
–16.8
0.07
–44
–
–
VSTAT(low)
ISTAT(pu)
INTh
INTl
VDD
µA
–20
0.7
–
–100
–
0.3
VDD
NOTES:
1. Upper logic threshold voltage applies to IN1, IN2, and SFPD and expressed in VDD units
3. Applies to IN1, IN2, and SFPD.
4. Initially have CEN = 0.7 x VDD, Ramp CEN down from VDD until IO = 0 and note disabling point.
5. Initially have Vin = 0.7 x VDD, Ramp CEN up from ground until IO = 0.1 A and note enabling point.
6. Applies equally to STAT1–2 and INT outputs; Measured threshold voltage by applying an “open” fault to OUT1 or OUT2 while forcing 600
µA
of
current into STAT1–2 or INT.
7. Measured with no faults on OUT1–2, VSTAT = VINT = 0.8 x VDD.
8. The Interrupt output has an internal active current pull–up
.
2. Lower logic threshold voltage applies to IN1, IN2, and SFPD and expressed in VDD units.
DC ELECTRICAL CHARACTERISTICS
(Characteristics noted under conditions 9.0 V
≤
VPwr
≤
17 V, 4.5 V
≤
VDD 5.5 V,
–40°C
≤
TL
≤
125°C, unless otherwise noted, typical values represent approximate mean at TL = 25°C.)
Characteristic
OUTPUT DYNAMICS
Symbol
Min
Typ
Max
Unit
µs
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ÁÁÁ
Á
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á Á Á Á
Output Short Sense Time (Note 1)
tss
30
54
100
6.0
12
50
75
10
10
Output Short Refresh Time (Note 2)
tref
3.0
3.0
–
–
4.1
6.4
7.2
40
11
2.6
ms
ms
µs
Output Open Sense ON Time (Note 3)
tos(on)
tdlh
tdhl
Output Propagation Delay
Turn–On (Output Low to High) (Note 4)
Turn–Off (Output High to Low) (Note 5)
Output Slew Rate
Output Rising (Note 6)
Output Falling (Note 7)
V/µs
SRr
SRf
0.2
0.2
NOTES:
1. CEN = 0.7 x VDD, SFPD = 0.3 x VDD, RL = 0, Step Vin from 0.3 x VDD to 0.7 x VDD; Sense time measured from step until STAT = 0.2 x VDD.
2. CEN = IN1 = IN2 = 0.7 x VDD, RL = 0; Refresh time measured from output disable until output is re–enabled.
3. RL = “open”, Step Vin from ground to 0.7 x VDD, Open sense time measured from step until VSTAT
≤
0.2 x VDD.
4. RL = 12
Ω,
CL = 0.01
µF,
step Vin from VIL to VIH; Turn–On propagation measured from Vin = 0.5 x VDD until Vout = 2.0 V (see Figure 2).
5. RL = 12
Ω,
CL = 0.01
µF,
step Vin from VIH to VIL; Turn–Off propagation measured from Vout = VPwr –3.0 V until Vout = 2.0 V (see Figure 2).
6. RL = 12
Ω,
CL = 0.01
µF,
step Vin from VIL to VIH; Output Slew Rate measured from 2.0 V to VPwr – 3.0 V (see Figure 2).
7. RL = 12
Ω,
CL = 0.01
µF,
step Vin from VIH to VIL; Output Slew Rate measured from VPwr – 3.0 V to 2.0 V (see Figure 2).
4
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MOTOROLA ANALOG IC DEVICE DATA
MC33143
Freescale Semiconductor, Inc.
Figure 2. Output Response Waveform
5.0 V
IN1–2
0V
tdlh
VPwr
OUT1–2
0V
2.0 V
tSRr
tSRf
VPwr – 3.0 V
tdhl
50%
Freescale Semiconductor, Inc...
PIN FUNCTION DESCRIPTION
Pin
1, 12
Symbol
IN1, IN2
Description
INput 1 and INput 2 (IN1 and IN2) respectively determine the state of the corresponding output drivers
(OUT1 and OUT2) under normal operating conditions. When an input is high, it’s corresponding output
is active ON, and when low is disabled OFF. IN1 and IN2 have internal active pull–downs which allow a
floating input pin to be conservatively interpreted as a logic low, turning Off the output. An unused input
should be connected to ground.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
Á
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Á
Á
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Á
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ÁÁÁÁÁÁÁÁ
2
CEN
Chip Enable (CEN) input pin, when low, disables both outputs (OUT1 and OUT2) and places the device
in a “sleep mode” reducing the bias current required from VDD and VPwr. A falling edge of CEN causes
OUT1 and OUT2 to rapidly turn OFF. A falling edge of CEN should precede any VDD shutdown to allow
time OUT1 and OUT2 to be disabled. When CEN is low, INTerrupt (INT) and STATus 1 and 2 (STAT1–2)
will be tri–stated (high impedance). The CEN pin can also be used for power–on reset and under
voltage lockout to disable the outputs for power supply voltages less than 4.5 V. CEN is a dependent
input from the system microcontroller unit (MCU) or some other integrated circuit. It has an internal
pull–up resistor to VDD affording a floating pin to be interpreted as a logic high. Rpull–up is greater than
50 kΩ. If used externally, this pin should be connected to VDD.
3, 10
STAT1. STAT2
The STATus pins (STAT1–2) respectively indicate the presence of faults on OUT1–2. STAT1–2 will be
logic high during normal operation. A logic low will occur whenever an Open Load, Short–to–Ground,
Short–to–Supply (Battery), Thermal Limit, or Overvoltage Shutdown fault condition is experienced on a
corresponding output. STAT1–2 are both active low digital drivers. A 10 kΩ resistor between STAT1–2
and the system CPU may improve a Failure Mode Evaluation Analysis (FMEA) score if STAT1–2 are
externally shorted to VPwr. If unused, this pin should be left connected.
These pins are connected to the supply and provide load current to the DMOS outputs, are used
pumping the DMOS gates, and for Overvoltage shutdown detection of the DMOS. The DMOS outputs
will turn ON with 5.5 to 24 V applied to VPwr. VPwr is limited to –1.5 V for a maximum duration of
250 ms. A 10 nF de–coupling cap is recommended to be used from VPwr to Ground.
These eight pins constitute the circuits ground (Gnd) and also provide heatsinking for the DMOS output
transistors. Ground continuity is required for the outputs2 to turn ON.
This pin is to be connected to the 5.0 V logic supply of the system. A 10 nF de–coupling capacitor is
recommended from VDD to Gnd.
4, 9, 16,
21
VPwr
Á
Á
Á
Á
Á
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Á
Á
Á
Á Á
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Á
Á Á
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
5, 6, 7, 8,
17, 18,
19, 20
11
Gnd
VDD
13, 24
OUT1, OUT2
These pins are connected internally to the DMOS output transistors which source current into the
corresponding load. Each output incorporates dynamic clamping to accommodate inductive loads. In
addition, each output has independent short to ground detection and protection, current limit detection
and protection, thermal limit detection and protection, ON open load and or short to supply (battery)
detection. Neither output will turn ON if CEN is logic low. An unused output should be connected to a
10 kΩ load to prevent false fault reporting. A 1.0 nF filter capacitor may be used from OUT to Gnd to
provide dV/dt noise filtering.
MOTOROLA ANALOG IC DEVICE DATA
For More Information On This Product,
5
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