HSP45102
TM
Data Sheet
January 1999
File Number
2810.6
12-Bit Numerically Controlled Oscillator
The Intersil HSP45102 is Numerically Controlled Oscillator
(NCO12) with 32-bit frequency resolution and 12-bit output.
With over 69dB of spurious free dynamic range and worst
case frequency resolution of 0.009Hz, the NCO12 provides
significant accuracy for frequency synthesis solutions at a
competitive price.
The frequency to be generated is selected from two frequency
control words. A single control pin selects which word is used
to determine the output frequency. Switching from one
frequency to another occurs in one clock cycle, with a 6 clock
pipeline delay from the time that the new control word is
loaded until t3-he new frequency appears on the output.
Two pins, P0-1, are provided for phase modulation. They are
encoded and added to the top two bits of the phase
accumulator to offset the phase in 90
o
increments.
The 13-bit output of the Phase Offset Adder is mapped to
the sine wave amplitude via the Sine ROM. The output data
format is offset binary to simplify interfacing to D/A
converters. Spurious frequency components in the output
sinusoid are less than -69dBc.
The NCO12 has applications as a Direct Digital Synthesizer
and modulator in low cost digital radios, satellite terminals,
and function generators.
Features
• 33MHz, 40MHz Versions
• 32-Bit Frequency Control
• BFSK, QPSK Modulation
• Serial Frequency Load
• 12-Bit Sine Output
• Offset Binary Output Format
• 0.009Hz Tuning Resolution at 40MHz
• Spurious Frequency Components <-69dBc
• Fully Static CMOS
• Low Cost
Applications
• Direct Digital Synthesis
• Modulation
• PSK Communications
• Related Products
- HI5731 12-Bit, 100MHz D/A Converter
Ordering Information
PART NUMBER
HSP45102PC-33
HSP45102PC-40
HSP45102SC-33
HSP45102SC-40
HSP45102SI-33
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
-40 to 85
PACKAGE
28 Ld PDIP
28 Ld PDIP
28 Ld SOIC
28 Ld SOIC
28 Ld SOIC
PKG.
NO.
E28.6
E28.6
M28.3
M28.3
M28.3
Block Diagram
CLK
PO-1
MSB/LSB
SFTEN
SD
SCLK
FREQUENCY
CONTROL
SECTION
LOAD
TXFR
ENPHAC
SEL_L/M
32
32
PHASE
ACCUMULATOR
13
PHASE
OFFSET
ADDER
13
SINE
ROM
12
OUT0-11
3-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright
©
Intersil Corporation 2000
HSP45102
Pinout
28 LEAD PDIP, 28 LEAD SOIC
TOP VIEW
OUT6 1
OUT7 2
OUT8 3
OUT9 4
OUT10 5
OUT11 6
GND 7
V
CC
8
SEL_L/M 9
SFTEN 10
MSB/LSB 11
ENPHAC 12
SD 13
SCLK 14
28 OUT5
27 OUT4
26 OUT3
25 OUT2
24 OUT1
23 OUT0
22 V
CC
21 GND
20 P0
19 P1
18 LOAD
17 TXFR
16 CLK
15 GND
Pin Description
NAME
V
CC
GND
P0-1
CLK
SCLK
SEL_L/M
SFTEN
MSB/LSB
ENPHAC
SD
TXFR
I
I
I
I
I
I
I
I
I
TYPE
+5V power supply pin.
Ground
Phase modulation inputs (become active after a pipeline delay of four clocks). A phase shift of 0, 90,
180, or 270 degrees can be selected as shown in Table 1.
NCO clock. (CMOS level)
This pin clocks the frequency control shift register.
A high on this input selects the least significant 32 bits of the 64-bit frequency register as the input to
the phase accumulator; a low selects the most significant 32 bits.
The active low input enables the shifting of the frequency register.
This input selects the shift direction of the frequency register. A low on this input shifts in the data LSB
first; a high shifts in the data MSB first.
This pin, when low, enables the clocking of the Phase Accumulator. This input has a pipeline delay of
four clocks.
Data on this pin is shifted into the frequency register by the rising edge of SCLK when SFTEN is low.
This active low input is clocked onto the chip by CLK and becomes active after a pipeline delay of four
clocks. When low, the frequency control word selected by SEL_L/M is transferred from the frequency
register to the phase accumulator’s input register.
This input becomes active after a pipeline delay of five clocks. When low, the feedback in the phase
accumulator is zeroed.
Output data. OUT0 is LSB. Unsigned.
DESCRIPTION
LOAD
OUT0-11
I
O
All inputs are TTL level, with the exception of CLK.
Overline designates active low signals.
3-2
HSP45102
PHASE OFFSET ADDER
R.P0-1
P0-1
ENPHAC
TXFR
LOAD
CLK
4-DLY
R
E
G
R.P0-1
R.ENPHAC
R.TXFR
R.LOAD
CLK
R
E
G
/
‘0’
32
MUX
1
/ 32
A
D
D
E
R
/
13 MSBs
A
D
D
E
R
13
/
CLK
R
E
G
/
13
R
E
G
SINE
ROM
/
CLK
12
2-DLY
R
E
G
OUT0-11
FREQUENCY
CONTROL
SECTION
64-BIT
SHIFT
REG
SD
SCLK
SFTEN
MSB/LSB
SEL_L/M
/
/
1
32
32
FRCTRL
0-31
FRCTRL
32-63
R.LOAD
ACCUMULATOR
INPUT
REGISTER
/ 32
R.TXFR
CLK
MUX
R
E
G
/ 32
0
/ 32
/ 32
R
E
G
/ 32
0
R.ENPHAC
CLK
(HIGH SELECTS FRCTRL0-31, LOW SELECTS FRCTRL32-63)
PHASE ACCUMULATOR
FIGURE 1. NCO-12 FUNCTIONAL BLOCK DIAGRAM
Functional Description
The NCO12 produces a 12-bit sinusoid whose frequency
and phase are digitally controlled. The frequency of the sine
wave is determined by one of two 32-bit words. Selection of
the active word is made by SEL_L/M. The phase of the
output is controlled by the two-bit input P0-1, which is used
to select a phase offset of 0, 90, 180, or 270 degrees.
As shown in the Block Diagram, the NCO12 consists of a
Frequency Control Section, a Phase Accumulator, a Phase
Offset Adder and a Sine ROM. The Frequency Control
section serially loads the frequency control word into the
frequency register. The Phase Accumulator and Phase
Offset Adder compute the phase angle using the frequency
control word and the two phase modulation inputs. The Sine
ROM generates the sine of the computed phase angle. The
format of the 12-bit output is offset binary.
the phase modulation bits P0-1. The architecture is shown in
Figure 1. The most significant 13 bits of the 32-bit phase
accumulator are summed with the two-bit phase offset to
generate the 13-bit phase input to the Sine Rom. A value of
0 corresponds to 0
o
, a value of 1000 hexadecimal
corresponds to a value of 180
o
.
The phase accumulator advances the phase by the amount
programmed into the frequency control register. The output
frequency is equal to:
F
LO
=
(
N
×
F
CLK
⁄
2
32
),
or
(EQ. 1)
F
OUT
32
N
=
INT
---------------
2
,
F
CLK
(EQ. 2)
Frequency Control Section
The Frequency Control Section shown in Figure 1 serially
loads the frequency data into a 64-bit, bidirectional shift
register. The shift direction is selected with the MSB/LSB
input. When this input is high, the frequency control word on
the SD input is shifted into the register MSB first. When
MSB/LSB is low the data is shifted in LSB first. The register
shifts on the rising edge of SCLK when SFTEN is low. The
timing of these signals is shown in Figures 2A and 2B.
The 64 bits of the frequency register are sent to the Phase
Accumulator Section where 32 bits are selected to control
the frequency of the sinusoidal output.
where N is the 32 bits of frequency control word that is
programmed. INT[•] is the integer of the computation. For
example, if the control word is 20000000 hexadecimal and the
clock frequency is 30MHz, then the output frequency would
be F
CLK
/8, or 3.75MHz.
The frequency control multiplexer selects the least
significant 32 bits from the 64-bit frequency control register
when SEL_L/M is high, and the most significant 32 bits
when SEL_L/M is low. When only one frequency word is
desired, SEL_L/M and MSB/LSB must be either both high
or both low. This is due to the fact that when a frequency
control word is loaded into the shift register LSB first, it
enters through the most significant bit of the register. After
32 bits have been shifted in, they will reside in the 32 most
significant bits of the 64-bit register.
When TXFR is asserted, the 32 bits selected by the frequency
control multiplexer are clocked into the phase accumulator input
Phase Accumulator Section
The phase accumulator and phase offset adder compute the
phase of the sine wave from the frequency control word and
3-3
HSP45102
register. At each clock, the contents of this register are summed
with the current contents of the accumulator to step to the new
phase. The phase accumulator stepping may be inhibited by
holding ENPHAC high. The phase accumulator may be loaded
with the value in the input register by asserting LOAD, which
zeroes the feedback to the phase accumulator.
The phase adder sums the encoded phase modulation bits
P0-1 and the output of the phase accumulator to offset the
phase by 0, 90, 180 or 270 degrees. The two bits are
encoded to produce the phase mapping shown in Table 1.
This phase mapping is provided for direct connection to the
in-phase and quadrature data bits for QPSK modulation.
TABLE 1. PHASE MAPPING
P0-1 CODING
P1
0
0
1
1
P0
0
1
0
1
PHASE SHIFT (DEGREES)
0
90
270
180
ROM Section
The ROM section generates the 12-bit sine value from the
13-bit output of the phase adder. The output format is offset
binary and ranges from 001 to FFF hexadecimal, centered
around 800 hexadecimal.
SCLK
SD
SFTEN
0
1
2
61
62
63
MSB/LSB
FIGURE 2A. FREQUENCY LOADING ENABLED BY SFTEN
SCLK
SD
SFTEN
MSB/LSB
0
1
2
61
62
63
FIGURE 2B. FREQUENCY LOADING CONTROLLED BY SCLK
CLK
LOAD
TXFR
ENPHAC
SEL_L/M
OUT0-11
1
2
3
4
5
6
7
8
9
10
11
NEW
DATA
FIGURE 3. I/O TIMING
3-4
HSP45102
Absolute Maximum Ratings
T
A
= 25
o
C
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Lead Temperature (Soldering, 10s). . . . . . . . . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage Applied . . . . .GND -0.5V to V
CC
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range (Commercial, Industrial) . . +4.75V to +5.25V
Operating Temperature Range (Commercial) . . . . . . . . 0
o
C to 70
o
C
Operating Temperature Range (Industrial) . . . . . . . . -40
o
C to 85
o
C
Die Characteristics
Backside Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
CC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
Logical One Input Voltage
Logical Zero Input Voltage
High Level Clock Input
Low Level Clock Input
Output HIGH Voltage
Output LOW Voltage
Input Leakage Current
Standby Power Supply Current
Operating Power Supply Current
SYMBOL
V
IH
V
IL
V
IHC
V
ILC
V
OH
V
OL
I
I
I
CCSB
I
CCOP
TEST CONDITIONS
V
CC
= 5.25V
V
CC
= 4.75V
V
CC
= 5.25V
V
CC
= 4.75V
I
OH
= -400µA, V
CC
= 4.75V
I
OL
= +2.0mA, V
CC
= 4.75V
V
IN
= V
CC
or GND, V
CC
= 5.25V
V
IN
= V
CC
or GND, V
CC
= 5.25V, Note 4
f = 33MHz, V
IN
= V
CC
or GND
V
CC
= 5.25V, Notes 2 and 4
MIN
2.0
-
3.0
-
2.6
-
-10
-
-
MAX
-
0.8
-
0.8
-
0.4
10
500
99
UNITS
V
V
V
V
V
V
µA
µA
mA
Capacitance
T
A
= 25
o
C, Note 3
PARAMETER
SYMBOL
C
IN
C
O
TEST CONDITIONS
FREQ = 1MHz, V
CC
= Open. All measure-
ments are referenced to device ground
MIN
-
-
MAX
10
10
UNITS
pF
pF
Input Capacitance
Output Capacitance
NOTES:
2. Power supply current is proportional to operating frequency. Typical rating for I
CCOP
is 3mA/MHz.
3. Not tested, but characterized at initial design and at major process/design changes.
4. Output load per test load circuit with switch open and C
L
= 40pF.
3-5
工作这点儿事
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
