HSP43168
Data Sheet
November 1999
File Number
2808.8
Dual FIR Filter
The HSP43168 Dual FIR Filter consists of two independent
8-tap FIR filters. Each filter supports decimation from 1 to 16
and provides on-board storage for 32 sets of coefficients.
The Block Diagram shows two FIR cells each fed by a
separate coefficient bank and one of two separate inputs.
The outputs of the FIR cells are either summed or
multiplexed by the MUX/Adder. The compute power in the
FIR Cells can be configured to provide quadrature filtering,
complex filtering, 2-D convolution, 1-D/2-D correlations, and
interpolating/decimating filters.
The FIR cells take advantage of symmetry in FIR
coefficients by pre-adding data samples prior to
multiplication. This allows an 8-tap FIR to be implemented
using only 4 multipliers per filter cell. These cells can be
configured as either a single 16-tap FIR filter or dual 8-tap
FIR filters. Asymmetric filtering is also supported.
Decimation of up to 16 is provided to boost the effective number
of filter taps from 2 to 16 times. Further, the Decimation
Registers provide the delay necessary for fractional data
conversion and 2-D filtering with kernels to 16 x16.
The flexibility of the Dual is further enhanced by 32 sets of
user programmable coefficients. Coefficient selection may
be changed asynchronously from clock to clock. The ability
to toggle between coefficient sets further simplifies
applications such as polyphase or adaptive filtering.
The HSP43168 is a low power fully static design
implemented in an advanced CMOS process. The
configuration of the device is controlled through a standard
microprocessor interface.
Features
• Two Independent 8-Tap FIR Filters Configurable as a
Single 16-Tap FIR
• 10-Bit Data and Coefficients
• On-Board Storage for 32 Programmable Coefficient Sets
• Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or 10 x 19-Bit
Data and Coefficients
• Programmable Decimation to 16
• Programmable Rounding on Output
• Standard Microprocessor Interface
Applications
• Quadrature, Complex Filtering
• Image Processing
• Polyphase Filtering
• Adaptive Filtering
Ordering Information
PART NUMBER
HSP43168VC-33
HSP43168VC-40
HSP43168VC-45
HSP43168JC-33
HSP43168JC-40
HSP43168JC-45
HSP43168JI-40
HSP43168GC-45
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
-40 to 85
0 to 70
PACKAGE
100 Ld MQFP
100 Ld MQFP
100 Ld MQFP
84 Ld PLCC
84 Ld PLCC
84 Ld PLCC
84 Ld PLCC
84 Ld CPGA
PKG. NO.
Q100.14x20
Q100.14x20
Q100.14x20
N84.1.15
N84.1.15
N84.1.15
N84.1.15
G84.A
Block Diagram
10
CIN0 - 9
A0 - 8
WR
CSEL0 - 4
9
CONTROL/
CONFIGURATION
COEFFICIENT
BANK A
10
INA0 - 9
FIR CELL A
MUX
MUX
COEFFICIENT
BANK B
FIR CELL B
INB0 - 9/
OUT0 - 8
10
MUX /
ADDER
9
OEL
OEH
19
OUT9 - 27
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
HSP43168
Pin Description
SYMBOL
V
CC
GND
CIN0-9
A0-8
I
I
TYPE
V
CC
: +5V power supply pin.
Ground.
Control/Coefficient Data Bus. Processor interface for loading control data and coefficients. CIN0 is the LSB.
Control/Coefficient Address Bus. Processor interface for addressing Control and Coefficient Registers. A0 is the
LSB.
Control/Coefficient Write Clock. Data is latched into the Control and Coefficient Registers on the rising edge of
WR.
Coefficient Select. This input determines which of the 32 coefficient sets are to be used by FIR A and B. This input
is registered and CSEL0 is the LSB.
Input to FIR A. INA0 is the LSB.
Bidirectional Input for FIR B. INB0 is the LSB and is input only. When used as output, INB1-9 are the LSBs of the
output bus, and INB9 is the MSB of these bits.
19 MSBs of Output Bus. Data format is either unsigned or two's complement depending on configuration. OUT27
is the MSB.
Shift Enable. This active low input enables clocking of data into the part and shifting of data through the Decimation
Registers.
Forward ALU Input Enable. When active low, data from the forward decimation path is input to the ALUs through
the “a” input. When high, the “a” inputs to the ALUs are zeroed.
Reverse ALU Input Enable. When active low, data from the reverse decimation path is input to the ALUs through
the “b” input. When high, the “b” inputs to the ALUs are zeroed.
Data Transfer Control. This active low input switches the LIFO being read into the reverse decimation path with
the LIFO being written from the forward decimation path (see Figure 1).
Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 5 lists the various
configurations.
Clock. All inputs except those associated with the processor interface (CIN0-9, A0-8, WR) and the output enables
(OEL, OEH) are registered by the rising edge of CLK.
Output Enable Low. This three-state control enables the LSBs of the output bus to INB1-9 when OEL is low.
Output Enable High. This three-state control enables OUT9-27 when OEH is low.
Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator. A low on this input
latches the FIR Accumulator contents into the Output Holding Registers while zeroing the feedback pass in the
Accumulator.
DESCRIPTION
WR
I
CSEL0-4
I
INA0-9
INB0-9
I
I/O
OUT9-27
O
SHFTEN
I
FWRD
I
RVRS
I
TXFR
I
MUX0-1
I
CLK
I
OEL
OEH
ACCEN
I
I
I
4
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