HSP43881
TM
Data Sheet
May 1999
FN2758.4
Digital Filter
The HSP43881 is a video speed Digital Filter (DF) designed
to efficiently implement vector operations such as FIR digital
filters. It is comprised of eight filter cells cascaded internally
and a shift and add output stage, all in a single integrated
circuit. Each filter cell contains a 8 x 8-bit multiplier, three
decimation registers and a 26-bit accumulator. The output
stage contains an additional 26-bit accumulator which can
add the contents of any filter cell accumulator to the output
stage accumulator shifted right by 8 bits. The HSP43881 has
a maximum sample rate of 30MHz. The effective multiply
accumulate (mac) rate is 240MHz.
The HSP43881 DF can be configured to process expanded
coefficient and word sizes. Multiple DFs can be cascaded for
larger filter lengths without degrading the sample rate or a
single DF can process larger filter lengths at less than
30MHz with multiple passes. The architecture permits
processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter coefficients
are less than 1.0, making even larger filter lengths possible.
The DF provides for 8-bit unsigned or two’s complement
arithmetic, independently selectable for coefficients and
signal data.
Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates
of
1
/
2
,
1
/
3
or
1
/
4
the input sample rate. These registers also
provide the capability to perform 2-D operations such as
matrix multiplication and N x N spatial
correlations/convolutions for image processing applications.
Features
• Eight Filter Cells
• 0MHz to 30MHz Sample Rate
• 8-Bit Coefficients and Signal Data
• 26-Bit Accumulator Per Stage
• Filter Lengths Over 1000 Taps
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4
Applications
• 1-D and 2-D FIR Filters
• Radar/Sonar
• Adaptive Filters
• Echo Cancellation
• Complex Multiply-Add
• Sample Rate Converters
Ordering Information
PART
NUMBER
HSP43881JC-20
HSP43881JC-25
HSP43881JC-30
HSP43881GC-20
HSP43881GC-25
HSP43881GC-30
TEMP. RANGE
(
o
C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
PACKAGE
84 Ld PLCC
84 Ld PLCC
84 Ld PLCC
85 Ld PGA
85 Ld PGA
85 Ld PGA
PKG. NO.
N84.1.15
N84.1.15
N84.1.15
G85.A
G85.A
G85.A
Block Diagram
V
CC
DIENB
CIENB
DCMO - 1
ERASE
TCCI
CIN0 - 7
RESET
CLK
ADR0 - 2
RESET
CLK
SHADD
SENBL
SENBH
8
5
V
SS
DIN0 - DIN7 TCS
8
5
8
DF
FILTER
CELL 0
5
3
MUX
ADR0, ADR1, ADR2
2
26
OUTPUT
STAGE
2
SUM0 - 25
26
26
8
8
DF
FILTER
CELL 1
26
8
8
DF
FILTER
CELL 2
26
8
8
DF
FILTER
CELL 3
26
8
8
DF
FILTER
CELL 4
26
8
8
DF
FILTER
CELL 5
26
8
8
DF
FILTER
CELL 6
26
8
8
DF
FILTER
CELL 7
26
TCCO
8
COUT0 - 7
COENB
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
HSP43881
Pinouts
85 PIN GRID ARRAY (PGA)
TOP VIEW, PINS DOWN
1
A
V
SS
V
CC
2
COENB
3
V
CC
4
5
6
DIN6
7
DIN3
8
DIN0
9
TCCI
10
V
CC
CIN6
11
V
SS
CIN4
RESET DIN7
B
COUT7 TCCO ERASE TCS
ALIGN
PIN
DIN1
DIN2
CIENB
CIN7
C COUT5 COUT6
DIENB
DIN5
DIN4
CIN5
CIN3
V
CC
D COUT3 COUT4
CIN2
E COUT1
V
SS
COUT2
CIN1
CIN0 SENBL
F
G
V
SS
COUT0 SHADD
CLK
SUM0
V
CC
V
SS
ADR2 DCM0
SUM1 SUM3 SUM2
H
J
ADR1
V
CC
ADR0
SUM25
SUM20 SUM17 SUM16
SUM5 SUM4
SUM7
V
SS
K SENBH SUM24
V
SS
V
CC
SUM19
V
SS
SUM15 SUM12 SUM10 SUM8 SUM6
L
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14
V
CC
SUM13
V
SS
SUM11 SUM9
HSP43881
TOP VIEW, PINS UP
1
2
3
4
5
6
7
8
9
10
11
L
DCM1
K
SENBH
J
V
CC
H
ADR1
G
ADR2
F
V
SS
E
COUT1
D
COUT3
C
COUT5 COUT6
B
V
CC
A
V
SS
COENB
V
CC
RESET
DIN7
DIN6
DIN3
DIN0
CIN8
V
CC
V
SS
COUT7
COUT8
ERASE
DIN8
DIN1
DIN2
CIENB
CIN7
CIN6
CIN4
ALIGN
PIN
DIENB
DIN5
DIN4
CIN5
CIN3
COUT4
CIN2
V
CC
V
SS
COUT2
CIN1
CIN0
SENBL
COUT0
SHADD
SUM0
V
CC
V
SS
DCM0
CLK
SUM1
SUM3
SUM2
ADR0
SUM5
SUM4
SUM25
SUM20
SUM17
SUM16
SUM7
V
SS
SUM24
V
SS
V
CC
SUM19
V
SS
SUM15
SUM12
SUM10
SUM8
SUM6
SUM23
SUM22
SUM21
SUM18
SUM14
V
CC
SUM13
V
SS
SUM11
SUM9
2
HSP43881
Pinouts
(Continued)
84 LEAD PLCC PACKAGE
BOTTOM VIEW
SHADD
SENBH
ADDR0
ADDR1
ADDR2
COUT0
COUT1
COUT2
COUT3
COUT4
COUT5
SUM24
SUM25
DCM1
DCM0
V
CC
CLK
V
SS
11 10
SUM23
SUM22
V
CC
SUM21
SUM20
SUM19
SUM18
V
SS
SUM17
SUM16
V
CC
SUM15
SUM14
SUM13
SUM12
V
SS
SUM11
SUM10
SUM9
SUM8
SUM7
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
COUT6
COUT7
V
SS
TCCO
COENB
V
CC
ERASE
RESET
DIENB
TCS
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
CIENB
TCCI
V
CC
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
SUM6
SUM5
SUM4
SUM3
SUM2
SUM1
SUM0
NOTE: An overbar on a signal name represents an active LOW signal.
3
SENBL
CIN7
V
SS
V
SS
V
CC
V
CC
V
SS
V
CC
V
SS
V
SS
HSP43881
Pin Description
SYMBOL
V
CC
PIN
NUMBER
A3, A10, B1,
D11, F10, J1,
K4, L7
A1, A11, E2,
F1, E11, H11,
K3, K6, L9
G3
A58, B67, C67
I
I
TYPE
+5V Power Supply Input.
DESCRIPTION
V
SS
Power Supply Ground Input.
CLK
DIN0-7
The CLK input provides the DF system sample clock. The maximum clock frequency is 30MHz.
These eight inputs are the data sample input bus. Eight bit data samples are synchronously loaded
through these pins to the X register of each filter cell simultaneously. The DIENB signal enables
loading, which is synchronous on the rising edge of the clock signal.
The TCS input determines the number system interpretation of the data input samples on pins
DIN0-7 as follows:
TCS = Low
→
Unsigned Arithmetic.
TCS = High
→
Two's Complement Arithmetic.
The TCS signal is synchronously loaded into the X register in the same way as the DIN0-7
inputs.
A low on this enables the data sample input bus (DIN0-7) to all the filter cells. A rising edge of the
CLK signal occurring while DIENB is low will load the X register of every filter cell with the 8-bit value
present on DIN0-7. A high on this input forces all the bits of the data sample input bus to zero; a
rising CLK edge when DIENB is high will load the X register of every filter cell with all zeros. This
signal is latched inside the DF, delaying its effect by one clock internal to the DF. Therefore, it must
be low during the clock cycle immediately preceding presentation of the desired data on the
DIN0-7 inputs. Detailed operation is shown in later timing diagrams.
These eight inputs are used to input the 8-bit coefficients. The coefficients are synchronously loaded
into the C register of filter CELL 0 if a rising edge of CLK occurs while CIENB is low. The CIENB
signal is delayed by one clock as discussed below.
The TCCI input determines the number system interpretation of the coefficient inputs on pins CIN07
as follows:
TCCI = LOW E Unsigned Arithmetic.
TCCI = HIGH E Two's Complement Arithmetic.
The TCCI signal is synchronously loaded into the C register in the same way as the CIN0-7 inputs.
A low on this input enable the C register of every filter cell and the D registers (decimation) of every
filter cell according to the state of the DCM0-1 inputs. A rising edge of the CLK signal occurring while
CIENB is low will load the C register and appropriate D registers with the coefficient data present at
their inputs. This provides the mechanism for shifting the coefficients from cell to cell through the
device. A high on this input freezes the contents of the C register and the D registers ignoring the
CLK signal. This signal is latched and delayed by one clock internal to the DF. Therefore, it must be
low during the clock cycle immediately preceding presentation of the desired coefficient of the CIN0-
7 inputs. Detailed operation is shown in the Timing Diagrams Section.
These eight three-state outputs are used to output the 8-bit coefficients from filter cell 7. These
outputs are enabled by the COENB signal low. These outputs may be tied to the CIN0-7 inputs of
the same DF to recirculate the coefficients, or they may be tied to the CIN0-7 inputs of another DF
to cascade DFs for longer filter lengths.
The TCCO three-state output determines the number system representation of the coefficients
output on COUTO-7. It tracks the TCCI signal to this same DF. It should be tied to the TCCI input
of the next DF in a cascade of DFs for increased filter lengths. This signal is enabled by COENB low.
A low on the COENB input enables the COUT0-7 and the TCCO output. A high on this input places
all these outputs in their high impedance state.
TCS
B5
I
DIENB
C5
I
CIN0-7
B9-11,
C10-11, D10,
E9-10
A9
I
TCCI
I
CIENB
B8
I
COUT0-7
B2, C1-2,
D1-2, E1, E3,
F2
B3
O
TCCO
O
COENB
A2
I
4
HSP43881
Pin Description
SYMBOL
DCM0-1
(Continued)
PIN
NUMBER
G2, L1
TYPE
DESCRIPTION
These two inputs determine the use of the internal decimation registers as follows:
DCM0
Decimation Function
DCM1
0
0
Decimation Registers not used.
0
1
One Decimation Register is used.
1
0
Two Decimation Registers are used.
1
1
Three Decimation Registers are used.
The coefficients pass from cell to cell at a rate determined by the number of decimation registers
used. When no decimation registers are used, coefficients move from cell to cell on each clock.
When one decimation register is used, coefficients move from cell to cell on every other clock, etc.
These signals are latched and delayed by one clock internal to the DF.
SUM0-25
J2, J5-8, J10,
K2, K5-11,
L-26, L8,
L10-11
O
These 26 three-state outputs are used to output the results of the internal filter cell computations.
Individual filter cell results or the result of the shift and add output stage can be output. If an
individual filter cell result is to be output, the ADR0-2 signals select the filter cell result. The SHADD
signal determines whether the selected filter cell result or the output stage adder result is output.
The signals SENBH and SENBL enable the most significant and least significant bits of the SUM0-
25 result, respectively. Both SENBH and SENBL may be enabled simultaneously if the system has
a 26-bit or larger bus. However, individual enables are provided to facilitate use with a 16-bit bus.
A low on this input enables result bits SUM16-25. A high on this input places these bits in their high
impedance state.
A low on this input enables result bits SUM0-15. A high on this input places these bits in their high
impedance state.
These inputs select the one cell whose accumulator will be read through the output bus (SUM0-25)
or added to the output stage accumulator. They also determine which accumulator will be cleared
when ERASE is low. For selection of which accumulator to read through the output bus (SUM0-25)
or which to add to the output stage accumulator, these inputs are latched in the DF and delayed by
one clock internal to the device. If the ADR0-2 lines remain at the same address for more than one
clock, the output at SUM0-25 will not change to reflect any subsequent accumulator updates in the
addressed cell. Only the result available during the first clock, when ADR0-1 selects the cell, will be
output. This does not hinder normal operation since the ADR0-1 lines are changed sequentially.
This feature facilitates the interface with slow memories where the output is required to be fixed for
more than one clock.
The SHADD input controls the activation of the shift-and-add operation in the output stage. This
signal is latched in the DF and delayed by one clock internal to the device. A detailed explanation
is given in the DF Output Stage Section.
A low on this input synchronously clears all the internal registers, except the cell accumulators. It
can be used with ERASE to also clear all the accumulators simultaneously. This signal is latched in
the DF and delayed by one clock internal to the DF.
A low on this input synchronously clears the cell accumulator selected by the ADR0-1 signals. If
RESET is also low simultaneously, all cell accumulators are cleared.
Used for aligning chip in socket or printed circuit board. Must be left as a no connect in circuit.
SENBH
SENBL
ADR0-2
K1
E11
G1, H1-2
I
I
I
SHADD
F3
I
RESET
A4
I
ERASE
ALIGN PIN
B4
C3
I
Functional Description
The Digital Filter Processor (DF) is composed of eight filter cells
cascaded together and an output stage for combining or
selecting filte5r cell outputs (See Block Diagram). Each filter cell
contains a multiplier accumulator and several registers (Figure
1). Each 8-bit coefficient is multiplied by an 8-bit data sample,
with the result added to the 26-bit accumulator contents. The
coefficient output of each cell is cascaded to the coefficient
input of the next cell to its right.
COUT0-7. With no decimation, the coefficient moves directly
from the C register to the output, and is valid on the clock
following its entrance. When decimation is selected the
coefficient exit is delayed by 1, 2 or 3 clocks by passing through
one or more decimation registers (D1, D2 or D3).
The combination of D registers through which the coefficient
passes is determined by the state of DCM0 and DCM1. The
output signals (COUT0-7) are connected to the CIN0-7 inputs
of the next cell to its right. The COENB input signal enables the
COUT0-7 outputs of the right most cell to the COUT-07 pins of
the device.
DF Filter Cell
An 8-bit coefficient (CIN0-7) enters each cell through the C
register on the left and exits the cell on the right as signals
5
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