HSP43216
Data Sheet
January 1999
File Number
3365.7
Halfband Filter
The HSP43216 Halfband Filter addresses a wide variety of
applications by combining f
S
/4 (f
S
= sample frequency)
quadrature up/down convert circuitry with a fixed coefficient
halfband filter processor as shown in the block diagram.
These elements may be configured to operate in one of the
four following modes: decimate by 2 filtering of a real input
signal; interpolate by 2 filtering of a real input signal; f
S
/4
quadrature down conversion of a real input signal followed
by decimate-by-2 filtering to produce a complex analytic
signal; interpolate-by-2 filtering of a complex analytic signal
followed by f
S
/4 quadrature up conversion to produce a real
valued output.
The frequency response of the HSP43216's halfband filter
has a shape factor, (passband+transition band)/passband,
of 1.24:1 with 90dB of stopband attenuation. The passband
has less than 0.0003dB of ripple from 0f
S
to 0.2f
S
with
stopband attenuation of greater than 90dB from 0.3f
S
to
Nyquist. At 0.25f
S
the filter provides 6dB of attenuation.
The HSP43216 processes data streams with word widths up
to 16 bits and data rates up to 52 MSPS. The processing
throughput of the part is easily doubled to rates of up to 104
MSPS by using the part together with an external multiplexer
or demultiplexer. Programmable rounding is provided to
support output precisions from 8 bits to 16 bits.
Features
• Sample Rates to 52 MSPS
• Architected to Support Sample Rates to 104 MSPS Using
External Multiplexer
• Four Modes of Operation:
- Interpolate by 2 Filtering
- Decimate by 2 Filtering
- Quadrature to Real Signal Conversion
- f
S
/4 Quadrature Down Conversion Followed by
Decimate by 2 Filtering
• 16-Bit Inputs and Outputs
• 67-Tap Halfband FIR Filter with 20-Bit Coefficients
• Two’s Complement or Offset Binary Outputs
• Programmable Rounding on Outputs
• 1.24:1 Filter Shape Factor
• >90dB Stopband Attenuation
• <0.0003dB Passband Ripple
• Saturation Logic on Output
Applications
• Digital Down Conversion
• D/A and A/D pre/post Filtering
Ordering Information
PART
NUMBER
HSP43216GC-52
HSP43216JC-52
HSP43216VC-52
TEMP.
RANGE (
o
C)
0 to 70
0 to 70
0 to 70
PACKAGE
TYPE
85 Ld CPGA
84 Ld PLCC
100 Ld MQFP
PKG. NO.
G85.A
N84.1.15
Q100.14x20
• Tuning Bandwidth Expansion for HSP45116 and
HSP45106
Block Diagram
AIN0-15
INPUT DATA
FLOW
BIN0-15
CONTROLLER
f
S
/4
QUADRATURE
DOWN
CONVERT
PROCESSOR
67-TAP
HALFBAND
FILTER
PROCESSOR
f
S
/4
QUADRATURE
UP CONVERT
PROCESSOR
OUTPUT DATA
FLOW
CONTROLLER/
FORMATTER
BOUT0-15
AOUT0-15
SYNC
USB/LSB
MODE0-1
INT/EXT
RND0-2
FMT
OEA
OEB
CLK
3-193
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
HSP43216
Pinouts
85 PIN PGA
TOP VIEW
11
L
10
9
BOUT
12
BOUT
14
8
BOUT
10
BOUT
11
7
BOUT
8
BOUT
9
BOUT
7
6
GND
5
BOUT
4
4
BOUT
1
3
V
CC
2
GND
1
RND1
L
BOUT BOUT
15
13
AOUT AOUT
2
0
AOUT
3
GND
AOUT
1
AOUT4
K
BOUT
5
BOUT
6
BOUT BOUT
3
0
BOUT
2
OEB
RND2
BIN15
K
J
RND0
BIN14
J
H
BIN13
BIN12
H
G
AOUT7 AOUT6 AOUT8
AOUT AOUT5 AOUT9
10
AOUT AOUT
11
12
AOUT AOUT
14
15
GND
OEA
AIN9
AIN10
AIN14
MODE
0
AOUT
13
BIN8
BIN10
BIN9
G
F
BIN7
BIN6
BIN11
F
E
BIN3
BIN4
BIN5
E
D
BIN1
INDEX
PIN
CLK
USB/
LSB
SYNC
BIN2
D
C
BIN0
INT/
EXT
V
CC
1
C
B
V
CC
FMT
11
AIN0
AIN1
AIN4
AIN7
AIN6
AIN13
B
A
AIN2
10
AIN3
9
AIN5
8
AIN8
7
AIN11
6
AIN12
5
AIN15 MODE1 GND
4
3
2
A
PIN ‘A1’
ID
85 PIN PGA
BOTTOM VIEW
1
L
RND1
2
GND
3
V
CC
OEB
4
5
6
7
BOUT8
8
BOUT
10
BOUT
11
9
BOUT
12
10
BOUT
13
11
BOUT
15
AOUT2
L
BOUT1 BOUT4 GND
K
BIN15
RND2
BOUT0 BOUT3 BOUT5 BOUT9
BOUT
AOUT0
14
K
J
BIN14
RND0
BOUT2 BOUT6 BOUT7
AOUT1 AOUT3
J
H
BIN12
BIN13
AOUT4
GND
H
G
BIN9
BIN10
BIN8
AOUT8 AOUT6 AOUT7
AOUT
10
AOUT
11
AOUT
14
GND
G
F
BIN11
BIN6
BIN7
AOUT9 AOUT5
AOUT AOUT
13
12
AOUT
15
F
E
BIN5
BIN4
BIN3
E
D
BIN2
BIN1
USB/
LSB
SYNC
INDEX
PIN
CLK
D
C
BIN0
INT/
EXT
V
CC
1
AIN14
AIN10
AIN9
OEA
C
B
MODE AIN13
AIN6
AIN7
AIN4
AIN1
AIN0
V
CC
FMT
11
B
A
PIN ‘A1’
ID
GND
2
MODE1 AIN15
3
4
AIN12 AIN11
5
6
AIN8
7
AIN5
8
AIN3
9
AIN2
10
A
3-194
HSP43216
Pinouts
(Continued)
100 LEAD MQFP
TOP VIEW
CLK
GND
MODE1
MODE0
AIN15
AIN14
AIN13
AIN12
AIN11
AIN10
AIN9
AIN8
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
V
CC
NC
NC
NC
NC
SYNC
USB/LSB
INT/EXT
BIN0
BIN1
BIN2
BIN3
BIN4
BIN5
BIN6
BIN7
BIN8
BIN9
BIN10
BIN11
BIN12
BIN13
BIN14
BIN15
RND0
RND1
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
RND2
OEB
GND
V
CC
BOUT0
BOUT1
BOUT2
BOUT3
BOUT4
BOUT5
BOUT6
BOUT7
BOUT8
BOUT9
GND
BOUT10
BOUT11
BOUT12
BOUT13
BOUT14
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
NC
FMT
OEA
V
CC
GND
AOUT15
AOUT14
AOUT13
AOUT12
AOUT11
AOUT10
AOUT9
AOUT8
AOUT7
AOUT6
AOUT5
GND
AOUT4
AOUT3
AOUT2
AOUT1
AOUT0
NC
NC
NC
NC
BOUT15
3-195
HSP43216
Pinouts
(Continued)
84 LEAD PLCC
TOP VIEW
V
CC
CLK
GND
MODE1
MODE0
AIN15
AIN14
AIN13
AIN12
AIN11
AIN10
AIN9
AIN8
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
SYNC
USB/LSB
INT/EXT
BIN0
BIN1
BIN2
BIN3
BIN4
BIN5
BIN6
BIN7
BIN8
BIN9
BIN10
BIN11
BIN12
BIN13
BIN14
BIN15
RND0
RND1
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
FMT
OEA
V
CC
GND
AOUT15
AOUT14
AOUT13
AOUT12
AOUT11
AOUT10
AOUT9
AOUT8
AOUT7
AOUT6
AOUT5
GND
AOUT4
AOUT3
AOUT2
AOUT1
AOUT0
Pin Description
NAME
V
CC
GND
CLK
AIN0-15
BIN0-15
MODE0-1
INT/EXT
SYNC
TYPE
-
-
I
I
I
I
I
I
+5V Power.
Ground.
Clock Input. (CMOS LEVEL). f
S
is the frequency of CLK
Input Data Bus A. AIN0 is the LSB. Input data format is 16-bit Two’s Complement.
Input Data Bus B. BIN0 is the LSB. Input data format is 16-bit Two’s Complement.
The Mode Select Inputs set one of four operational modes as highlighted in Table 1.
The Internal\External multiplexer select inputs set whether the data multiplex/demultiplex function required in the various
operational modes is performed internally (High State) or externally to the chip (Low State).
This input is used to synchronize the input sample stream with the zero degree phase of the up or down convert Local
Oscillators. In the straight decimate modes, this input can be use to synchronize the input sample stream with a particular
phase of the halfband filter. (See the Operational Modes Section for additional information).
The Upper and Lower Sideband select line is used to specify the direction of frequency translation imparted on the data
stream in the Down Convert and Decimate Mode and in the Quadrature to Real Convert Mode. (See Operational Modes
Section for additional information).
The Round Select inputs set the number of output bits from eight (RND = 000) to sixteen (RND = 110). Least significant
output bits are zeroed. See Table 4.
Three-State Control Output Bus A, OUTA0-15. Active Low.
Three-State Control Output Bus B, OUTB0-15. Active Low.
The Format select input is used to convert the two’s complement output to offset binary (unsigned). When asserted high,
the AOUT15 and BOUT15 bits are inverted from the normal two’s complement representation.
Output Bus A. AOUT0 is the LSB.
Output Bus B. BOUT0 is the LSB.
DESCRIPTION
USB/LSB
I
RND0-2
OEA
OEB
FMT
AOUT0-15
BOUT0-15
I
I
I
I
O
O
3-196
RND2
OEB
GND
V
CC
BOUT0
BOUT1
BOUT2
BOUT3
BOUT4
BOUT5
BOUT6
BOUT7
BOUT8
BOUT9
GND
BOUT10
BOUT11
BOUT12
BOUT13
BOUT14
BOUT15
HSP43216
f
S
/4 QUADRATURE
DOWN CONVERT
PROCESSOR
67-TAP HALFBAND
FILTER
PROCESSOR
f
S
/4 QUADRATURE
UP CONVERT
PROCESSOR
INPUT DATA FLOW
CONTROLLER
OUTPUT DATA FLOW
CONTROLLER
R
E
G
†
AIN0-15
R
E
G
R
E
G
R
E
G
†
R
E
G
†
DELAY 2 - 35
EVEN TAP
FILTER
SYNC
USB/LSB
PIPELINE
†
R
E
G
M
U
X
R F R R
N M E E
D T G G
AOUT0-15
MUX
1
1
MUX
1,-1,1,..
-1,1,-1,.
MUX
...,2,-2,2
..,-2,2,-2
1 2
1 2
MUX
OEA
f
S
/4
L.O.
+
†
BIN0-15
R R
E E
G G
M
U
X
R
E
G
†
R
E
G
†
PIPELINE
DELAY 19
†
R
E
G
R F R R
N M E E
D T G G
BOUT0-15
ODD TAP
FILTER
OEB
CLK
MODE0-1
SYNC
INT/EXT
RND0-2
FMT
USB/LSB
†
Indicates elements which operate at CLK/2 when the INT/EXT control input is high.
FIGURE 1. HALFBAND BLOCK DIAGRAM
Functional Description
The operation of the HSP43216 centers around a fixed
coefficient, 67-Tap, Halfband Filter Processor as shown in
Figure 1. The Halfband Filter Processor operates stand
alone to provide two fundamental modes of operation:
interpolate or decimate by two filtering of a real signal. In two
other modes, the Quadrature Up/Down Convert circuitry
operates together with the Filter Processor block to provide
f
S
/4 Down Conversion with decimate by 2 filtering or
Quadrature to Real Conversion.
In Down Convert and Decimate mode, a real input sample
stream is spectrally shifted by f
S
/4. Each component of the
resulting complex signal is then halfband filtered and
decimated by 2 to produce real and imaginary output
samples at half of the input data rate.
In Quadrature to Real Conversion mode, the real and
imaginary components of a quadrature input are interpolated
by two and halfband filtered. The filtered result is then
spectrally shifted by f
S
/4 and the real component of this
operation is output at twice the input sample rate.The
HSP43216 is configured for different operational modes by
setting the state of the mode control pins, MODE1-0 as
shown in Table 1.
00
01
10
11
TABLE 1. MODE SELECT TABLE
MODE1-0
Decimate by Two
Interpolate by Two
Down Convert and Decimate
Quadrature to Real Conversion
MODE
Input Data Flow Controller
The Input Data Flow Controller routes data samples from the
AIN0-15 and BIN0-15 inputs to the internal processing
elements of the Halfband. The data routing paths are based
on mode of operation and are more fully discussed in the
Operational Modes section.
f
S
/4 Quadrature Down Convert Processor
The f
S
/4 Quadrature Down Convert Processor operates as a
Quadrature LO which provides the negative f
S
/4 spectral
shift required to center the upper sideband of a real input
signal at DC. This operation is equivalent to multiplying the
real sample stream, x(n), by the quadrature components of
the complex exponential e
-j(π/2)n
as given below:
x
(
n
)
e
–
j
(
πn
⁄
2
)
=
x
(
n
)
cos
(
πn
⁄
2
)
+
jx
(
n
)
sin
(
–
π
n
⁄
2
)
(EQ. 1)
3-197
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