HSP43220
TM
Data Sheet
September 2000
File Number
2486.8
Decimating Digital Filter
The HSP43220 Decimating Digital Filter is a linear phase
low pass decimation filter which is optimized for filtering
narrow band signals in a broad spectrum of a signal
processing applications. The HSP43220 offers a single chip
solution to signal processing applications which have
historically required several boards of ICs. This reduction in
component count results in faster development times as well
as reduction of hardware costs.
The HSP43220 is implemented as a two stage filter
structure. As seen in the block diagram, the first stage is a
high order decimation filter (HDF) which utilizes an efficient
sample rate reduction technique to obtain decimation up to
1024 through a coarse low-pass filtering process. The HDF
provides up to 96dB aliasing rejection in the signal pass
band. The second stage consists of a finite impulse
response (FIR) decimation filter structured as a transversal
FIR filter with up to 512 symmetric taps which can implement
filters with sharp transition regions. The FIR can perform
further decimation by up to 16 if required while preserving
the 96dB aliasing attenuation obtained by the HDF. The
combined total decimation capability is 16,384.
The HSP43220 accepts 16-bit parallel data in 2’s
complement format at sampling rates up to 33 MSPS. It
provides a 16-bit microprocessor compatible interface to
simplify the task of programming and three-state outputs to
allow the connection of several ICs to a common bus. The
HSP43220 also provides the capability to bypass either the
HDF or the FIR for additional flexibility.
Features
• Single Chip Narrow Band Filter with up to 96dB
Attenuation
• DC to 33MHz Clock Rate
• 16-Bit 2’s Complement Input
• 20-Bit Coefficients in FIR
• 24-Bit Extended Precision Output
• Programmable Decimation up to a Maximum of 16,384
• Standard 16-Bit Microprocessor Interface
• Filter Design Software Available DECIMATE™
• Up to 512 Taps
Applications
• Very Narrow Band Filters
• Zoom Spectral Analysis
• Channelized Receivers
• Large Sample Rate Converter
Ordering Information
PART NUMBER
HSP43220VC-33
HSP43220JC-25
HSP43220JC-33
HSP43220GC-25
HSP43220GC-33
TEMP.
RANGE (
o
C)
0 to 70
0 to 0
0 to 70
0 to 70
0 to 70
PACKAGE
100 Ld MQFP
84 Ld PLCC
84 Ld PLCC
84 Ld CPGA
84 Ld CPGA
PKG. NO.
Q100.14x20
N84.1.15
N84.1.15
G84.A
G84.A
DECIMATE
Software Development Tool (This software tool may be
downloaded from our Internet site: http://www.intersil.com)
Block Diagram
DECIMATION UP TO 1024
INPUT CLOCK
DATA INPUT
CONTROL AND COEFFICIENTS
HIGH ORDER
DECIMATION
FILTER
DECIMATION UP TO 16
FIR
DECIMATION
FILTER
FIR CLOCK
24
DATA OUT
DATA READY
16
16
3-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright © Intersil Corporation 2000
DECIMATE™ is a trademark of Intersil Corporation.
HSP43220
Pinouts
84 PIN GRID ARRAY (PGA)
1
2
DATA_
IN 1
START
OUT
V
CC
3
DATA_
IN 2
DATA_
IN 0
4
DATA_
IN 4
DATA_
IN 3
5
DATA_
IN 7
DATA_
IN 6
DATA_
IN 5
6
DATA_
IN 8
DATA_
IN 13
DATA_
IN 9
7
DATA_
IN 11
DATA_
IN 12
DATA_
IN 10
8
DATA_
IN 14
DATA_
IN 15
9
10
GND
11
GND
DATA_
OUT 1
DATA_
OUT 2
DATA_
OUT 4
DATA_
OUT 7
DATA_
OUT 8
DATA_
OUT 11
A
GND
START
IN
ASTART
IN
A1
V
CC
B
CK_IN
V
CC
DATA_
OUT 0
DATA_
OUT 3
C
D
RESET
E
CS
WR
A0
HSP43220
F
C_BUS
10
C_BUS
12
C_BUS
9
C_BUS C_BUS
15
14
C_BUS C_BUS
11
13
V
CC
C_BUS
7
C_BUS
5
C_BUS
3
C_BUS C_BUS
4
1
C_BUS C_BUS
2
0
OUT_
SELH
OUT_
ENP
OUT_
ENX
FIR_
CK
GND
DATA_
OUT 5
DATA_
OUT 9
DATA_
OUT 10
DATA_
OUT 6
V
CC
TOP VIEW
PINS DOWN
G
GND
H
DATA_ DATA_
OUT 13 OUT 12
DATA_ DATA_
OUT 16 OUT 14
DATA_ DATA_ DATA_ DATA_
OUT 22 OUT 19 OUT 17 OUT 15
DATA_ DATA_ DATA_ DATA_
OUT 23 OUT 21 OUT 20 OUT 18
J
GND
C_BUS
8
C_BUS
6
GND
K
V
CC
DATA_
RDY
L
V
CC
1
L
2
3
4
5
6
7
8
9
10
11
C_BUS C_BUS
6
3
K
C_BUS C_BUS
8
5
J
GND
H
C_BUS
9
G
C_BUS C_BUS
12
11
F
C_BUS C_BUS
15
10
E
CS
D
A1
C
ASTART
IN
B
START START
IN
OUT
A
GND
DATA_
IN 1
V
CC
RESET
WR
V
CC
C_BUS
7
C_BUS
2
C_BUS
4
C_BUS OUT_
0
ENX
C_BUS OUT_
1
ENP
OUT_
SELH
DATA_
RDY
V
CC
V
CC
DATA_ DATA_ DATA_ DATA_
OUT 23 OUT 21 OUT 20 OUT 18
DATA_ DATA_ DATA_ DATA_
OUT 22 OUT 19 OUT 17 OUT 15
DATA_ DATA_
OUT 16 OUT 14
DATA_ DATA_
OUT 13 OUT 12
GND
GND
FIR_
CK
C_BUS
13
C_BUS
14
A0
HSP43220
BOTTOM VIEW
PINS UP
DATA_
OUT 10
DATA_
OUT 9
DATA_
OUT 5
GND
DATA_
OUT 11
DATA_
OUT 8
DATA_
OUT 7
DATA_
OUT 4
DATA_
OUT 2
DATA_
OUT 1
GND
V
CC
DATA_
OUT 6
DATA_
OUT 3
DATA_ DATA_
IN 9
IN 5
DATA_
IN 0
DATA_
IN 2
DATA_ DATA_ DATA_
IN 3
IN 6
IN 13
DATA_ DATA_ DATA_
IN 4
IN 7
IN 8
DATA_
IN 10
DATA_
IN 12
DATA_
IN 11
DATA_
IN 15
DATA_
IN 14
DATA_
OUT 0
V
CC
CK_IN
V
CC
GND
3-2
HSP43220
Pinouts
(Continued)
100 LEAD MQFP
TOP VIEW
DATA_IN0
DATA_IN1
DATA_IN2
DATA_IN3
DATA_IN4
DATA_IN5
DATA_IN6
DATA_IN7
DATA_IN8
DATA_IN9
DATA_IN10
DATA_IN11
DATA_IN12
DATA_IN13
DATA_IN14
DATA_IN15
V
CC
V
CC
GND
GND
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
GND
GND
NC
STARTOUT
V
CC
V
CC
STARTIN
ASTARTIN
RESET
A1
A0
WR
CS
C_BUS15
C_BUS14
C_BUS13
C_BUS12
C_BUS11
C_BUS10
C_BUS9
V
CC
V
CC
GND
GND
C_BUS8
C_BUS7
C_BUS6
NC
C_BUS5
C_BUS4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
C_BUS3
C_BUS2
C_BUS1
C_BUS0
OUT_SELH
OUT_ENP
OUT_ENX
V
CC
V
CC
GND
GND
FIR_CK
V
CC
V
CC
GND
GND
DATA_RDY
DATA_OUT23
DATA_OUT22
DATA_OUT21
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CK_IN
V
CC
V
CC
GND
GND
DATA_OUT0
DATA_OUT1
DATA_OUT2
DATA_OUT3
DATA_OUT4
DATA_OUT5
DATA_OUT6
DATA_OUT7
DATA_OUT8
DATA_OUT9
DATA_OUT10
DATA_OUT11
GND
GND
V
CC
V
CC
DATA_OUT12
DATA_OUT13
DATA_OUT14
DATA_OUT15
DOUT_OUT16
DATA_OUT17
DATA_OUT18
DATA_OUT19
DATA_OUT20
3-3
HSP43220
Pinouts
(Continued)
84 PLASTIC LEADED CHIP CARRIER (PLCC)
GND
DATA_IN 0
DATA_IN 1
DATA_IN 2
DATA_IN 3
DATA_IN 4
DATA_IN 5
DATA_IN 6
DATA_IN 7
DATA_IN 8
DATA_IN 9
DATA_IN 10
DATA_IN 11
DATA_IN 12
DATA_IN 13
DATA_IN 14
DATA_IN 15
V
CC
GND
CK_IN
V
CC
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
STARTOUT
V
CC
STARTIN
ASTARTIN
RESET
A1
A0
WR
CS
C_BUS 15
C_BUS 14
C_BUS 13
C_BUS 12
C_BUS 11
C_BUS 10
C_BUS 9
V
CC
GND
C_BUS 8
C_BUS 7
C_BUS 6
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
C_BUS 5
C_BUS 4
C_BUS 3
C_BUS 2
C_BUS 1
C_BUS 0
OUT_SELH
OUT_ENP
OUT_ENX
V
CC
GND
FIR_CK
V
CC
GND
DATA_RDY
DATA_OUT 23
DATA_OUT 22
DATA_OUT 21
DATA_OUT 20
DATA_OUT 19
DATA_OUT 18
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
GND
DATA_OUT 0
DATA_OUT 1
DATA_OUT 2
DATA_OUT 3
DATA_OUT 4
DATA_OUT 5
DATA_OUT 6
DATA_OUT 7
DATA_OUT 8
DATA_OUT 9
DATA_OUT 10
DATA_OUT 11
GND
V
CC
DATA_OUT 12
DATA_OUT 13
DATA_OUT 14
DATA_OUT 15
DATA_OUT 16
DATA_OUT 17
Pin Description
NAME
V
CC
GND
CK_IN
I
TYPE
The +5V power supply pins.
The device ground.
Input Sample Clock. Operations in the HDF are synchronous with the rising edge of this clock signal. The maximum clock
frequency is 33MHz. CK_IN is synchronous with FIR_CK and thus the two clocks may be tied together if required, or CK_IN
can be divided down from FIR_CK. CK_IN is a CMOS level signal.
Input Clock for the FIR Filter. This clock must be synchronous with CK_IN. Operations in the FIR are synchronous with the
rising edge of this clock signal. The maximum clock frequency is 33MHz. FIR_CK is a CMOS level signal.
Input Data Bus. This bus is used to provide the 16-bit input data to the HSP43220. The data must be provided in a synchro-
nous fashion, and is latched on the rising edge of the CK_IN signal. The data bus is in 2's complement fractional format. Bit
15 is the MSB.
Control Input Bus. This input bus is used to load all the filter parameters. The pins WR, CS and A0, A1 are used to select
the destination of the data on the Control bus and write the Control bus data into the appropriate register as selected by A0
and A1
Output Data Bus. This 24-Bit output port is used to provide the filtered result in 2's complement format. The upper 8 bits of
the output, DATA_OUT16-23 will provide extension or growth bits depending on the state of OUT_SELH and whether the
FIR has been put in bypass mode. Output bits DATA_OUT0-15 will provide bits 20 through 2-15 when the FIR is not by-
passed and will provide the bits 2-16 through 2-31 when the FIR is in bypass mode.
An active high output strobe that is synchronous with FIR_CK that indicates that the result of the just completed FIR cycle
is available on the data bus.
RESET is an asynchronous signal which requires that the input clocks CK_IN and FIR_CK are active when RESET is as-
serted. RESET disables the clock divider and clears all of the internal data registers in the HDF. The FIR filter data path is
not initialized. The control register bits that are cleared are F_BYP, H_STAGES, and H_DRATE. The F_DIS bit is set. In order
to guarantee consistent operation of the part, the user must reset the DDF after power up.
Write Strobe. WR is used for loading the internal registers of the HSP43220. When CS and WR are asserted, the rising edge of
WR will latch the C_BUS0-15 data into the register specified by A0 and A1.
Chip Select. The Chip Select input enables loading of the internal registers. When CS and WR are low, the A0 and A1 address
lines are decoded to determine the destination of the data on C_BUS0-15. The rising edge of WR then loads the appropriate
register as specified by A0 and A1.
DESCRIPTION
FIR_CK
DATA_IN0-15
I
I
C_BUS0-15
I
DATA_OUT
0-23
O
DATA_RDY
RESET
O
I
WR
CS
I
I
3-4
HSP43220
Pin Description
NAME
A0, A1
ASTARTIN
STARTOUT
TYPE
I
I
O
(Continued)
DESCRIPTION
Control Register Address. These lines are decoded to determine which control register is the destination for the data on
C_BUS0-15. Register loading is controlled by the A0 and A1, WR and CS inputs.
ASTARTIN is an asynchronous signal which is sampled on the rising edge of CK_IN. It is used to put the DDF in operational
mode. ASTARTIN is internally synchronized to CK_IN and is used to generate STARTOUT.
STARTOUT is a pulse generated from the internally synchronized version of ASTARTIN. It is provided as an output for use
in multi-chip configurations to synchronously start multiple HSP43220's. The width of STARTOUT is equal to the period of
CK_IN.
STARTIN is a Synchronous Input. A high to low transition of this signal is required to start the part. STARTIN is sampled on
the rising edge of CK_IN. This synchronous signal can be used to start single or multiple HSP43220's.
Output Select. The OUT_SELH input controls which bits are provided at output pins DATA_OUT16-23. A HIGH on this control
line selects bits 28 through 21 from the accumulator output. A LOW on this control line selects bits 2-16 through 2-23 from
the accumulator output. Processing is not interrupted by this pin.
Output Enable. The OUT_ENP input controls the state of the lower 16 bits of the output data bus, DATA_OUT0-15. A LOW on
this control line enables the lower 16 bits of the output bus. When OUT_ENP is HIGH, the output drivers are in the high imped-
ance state. Processing is not interrupted by this pin.
Output Enable. The OUT_ENX input controls the state of the upper 8 bits of the output data bus, DATA_OUT16-23. A LOW
on this control line enables the upper 8 bits of the output bus. When OUT_ENX is HIGH, the output drivers are in the high
impedance state. Processing is not interrupted by this pin.
STARTIN
OUT_SELH
I
I
OUT_ENP
I
OUT_ENX
I
The HDF
The first filter section is called the High Order Decimation Filter
(HDF) and is optimized to perform decimation by large factors.
It implements a low pass filter using only adders and delay
elements instead of a large number of multiplier/ accumulators
that would be required using a standard FIR filter.
The HDF is divided into 4 sections: the HDF filter section,
the clock divider, the control register logic and the start logic
(Figure 1).
Integrator Section
The data from the shifter goes to the Integrator section.
This is a cascade of 5 integrator (or accumulator) stages,
which implement a low pass filter. Each accumulator is
implemented as an adder followed by a register in the feed
forward path. The integrator is clocked by the sample clock,
CK_IN as shown in Figure 2. The bit width of each integrator
stage goes from 66 bits at the first integrator down to 26 bits
at the output of the fifth integrator. Bit truncation is performed
at each integrator stage because the data in the integrator
stages is being accumulated and thus is growing, therefore
the lower bits become insignificant, and can be truncated
without losing significant data.
Data Shifter
After being latched into the Input Register the data enters the
Data Shifter. The data is positioned at the output of the shifter
to prevent errors due to overflow occurring at the output of the
HDF. The number of bits to shift is controlled by H_GROWTH.
A0-1
WR
CS
C_BUS
H_DRATE
CK_IN
RESET
RESET
CK_IN ASTARTIN
STARTIN
CONTROL
REGISTER LOGIC
H_BYP
CLOCK
DIVIDER
ISTART
START
LOGIC
STARTOUT
6
H_GROWTH
5
INT_EN1-5
5
COMB_EN1-5
CK DEC
HDF FILTER SECTION
ISTART
H_GROWTH
6
DATA
IN 16
INPUT
REG 16
DATA
SHIFTER 66
INT_EN1-5
5
INTEGRATOR
DEC
REG 26
RESET
COMB_EN1-5
5
TO FIR
COMB FILTER
19
ROUND
16
REG
16
RESET
26
CK_IN
CK_DEC
TO FIR
FIGURE 1. HIGH ORDER DECIMATION FILTER FIGURE
3-5
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