S E M I C O N D U C T O R
HD-6402
CMOS Universal Asynchronous
Receiver Transmitter (UART)
Description
The HD-6402 is a CMOS UART for interfacing computers or
microprocessors to an asynchronous serial data channel.
The receiver converts serial start, data, parity and stop bits.
The transmitter converts parallel data into serial form and
automatically adds start, parity and stop bits. The data word
length can be 5, 6, 7 or 8 bits. Parity may be odd or even.
Parity checking and generation can be inhibited. The stop
bits may be one or two or one and one-half when transmit-
ting 5-bit code.
The HD-6402 can be used in a wide range of applications
including modems, printers, peripherals and remote data
acquisition systems. Utilizing the Harris advanced scaled
SAJI IV CMOS process permits operation clock frequencies
up to 8.0MHz (500K Baud). Power requirements, by compar-
ison, are reduced from 300mW to 10mW. Status logic
increases flexibility and simplifies the user interface.
March 1997
Features
• 8.0MHz Operating Frequency (HD-6402B)
• 2.0MHz Operating Frequency (HD-6402R)
• Low Power CMOS Design
• Programmable Word Length, Stop Bits and Parity
• Automatic Data Formatting and Status Generation
• Compatible with Industry Standard UARTs
• Single +5V Power Supply
• CMOS/TTL Compatible Inputs
Ordering Information
PACKAGE
Plastic DIP
CERDIP
SMD#
TEMPERATURE RANGE
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-55
o
C to +125
o
C
2MHz = 125K BAUD
HD3-6402R-9
HD1-6402R-9
5962-9052501MQA
8MHz = 500K BAUD
HD3-6402B-9
HD1-6402B-9
5962-9052502MQA
PKG. NO.
E40.6
F40.6
F40.6
Pinout
HD-6402 (PDIP, CERDIP)
TOP VIEW
V
CC
NC
GND
RRD
RBR8
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
PE
FE
OE
SFD
RRC
DRR
DR
RRI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 TRC
39 EPE
38 CLS1
37 CLS2
36 SBS
35 PI
34 CRL
33 TBR8
32 TBR7
31 TBR6
30 TBR5
29 TBR4
28 TBR3
27 TBR2
26 TBR1
25 TRO
24 TRE
23 TBRL
22 TBRE
21 MR
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1997
File Number
2956.1
5-100
HD-6402
Functional Diagram
(32)
TBR8
(33)
(31)
(30)
(29)
(28)
(27)
(26)
TBR1
(24) TRE
(22) TBRE
†
(23) TBRL
(40) TRC
TRANSMITTER
TIMING AND
CONTROL
PARITY
LOGIC
TRANSMITTER BUFFER REGISTER
STOP
TRANSMITTER REGISTER
MULTIPLEXER
(25) TRO
START
(38) CLS1
(37) CLS2
(34) CRL
(21) MR
CONTROL
REGISTER
(36) SBS
(16) SFD
(39) EPE
(35) PI
(20) RRI
(17) RRC
(18) DRR
(19) DR
†
RECEIVER
TIMING AND
CONTROL
STOP
LOGIC
PARITY
LOGIC
MULTIPLEXER
RECEIVER REGISTER
RECEIVER BUFFER REGISTER
3-STATE
BUFFERS
†
RBR8
START
LOGIC
(16) SFD
†
THESE OUTPUTS ARE
THREE-STATE
(4) RRD
†
RBR1
(5) (6) (7) (8) (9) (10) (11) (12)
†
OE
(15)
†
FE
(14)
†
PE
(13)
Control Definition
CONTROL WORD
CLS 2
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
CLS 1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
PI
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
EPE
0
0
1
1
X
X
0
0
1
1
X
x
0
0
1
1
X
x
0
0
1
1
X
x
SBS
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
START BIT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CHARACTER FORMAT
DATA BITS
5
5
5
5
5
5
6
6
6
6
6
6
7
7
7
7
7
7
8
8
8
8
8
8
PARITY BIT
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
STOP BITS
1
1.5
1
1.5
1
1.5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
5-101
HD-6402
Pin Description
PIN TYPE SYMBOL
1
2
3
4
I
V
CC
†
NC
GND
RRD
DESCRIPTION
Positive Voltage Supply
No Connection
Ground
A high level on RECEIVER REGISTER DISABLE
forces the receiver holding out-puts RBR1-RBR8
to high impedance state.
The contents of the RECEIVER BUFFER REGIS-
TER appear on these three-state outputs. Word for-
mats less than 8 characters are right justified to
RBR1.
See Pin 5-RBR8
See Pin 5-RBR8
See Pin 5-RBR8
See Pin 5-RBR8
See Pin 5-RBR8
See Pin 5-RBR8
See Pin 5-RBR8
A high level on PARITY ERROR indicates received
parity does not match parity programmed by control
bits. When parity is inhibited this output is low.
A high level on FRAMING ERROR indicates the
first stop bit was invalid.
A high level on OVERRUN ERROR indicates the
data received flag was not cleared before the last
character was transferred to the receiver buffer
register.
A high level on STATUS FLAGS DISABLE forces
the outputs PE, FE, OE, DR, TBRE to a high im-
pedance state.
The Receiver register clock is 16X the receiver
data rate.
A low level on DATA RECEIVED RESET clears
the data received output DR to a low level.
A high level on DATA RECEIVED indicates a
character has been received and transferred to
the receiver buffer register.
Serial data on RECEIVER REGISTER INPUT is
clocked into the receiver register.
A high level on MASTER RESET clears PE, FE,
OE and DR to a low level and sets the transmitter
register empty (TRE) to a high level 18 clock cycles
after MR falling edge. MR does not clear the receiv-
er buffer register. This input must be pulsed at least
once after power up. The HD-6402 must be master
reset after power up. The reset pulse should meet
V
IH
and t
MR
. Wait 18 clock cycles after the falling
edge of MR before beginning operation.
27
28
29
30
31
32
33
34
I
I
I
I
I
I
I
I
TBR2
TBR3
TBR4
TBR5
TBR6
TBR7
TBR8
CRL
26
I
TRB1
25
O
TRO
24
O
TRE
23
I
TBRL
PIN TYPE SYMBOL
22
O
TBRE
DESCRIPTION
A high level on TRANSMITTER BUFFER REGIS-
TER EMPTY indicates the transmitter buffer register
has transferred its data to the transmitter register
and is ready for new data.
A low level on TRANSMITTER BUFFER REGIS-
TER LOAD transfers data from inputs TBR1-
TBR8 into the transmitter buffer register. A low to
high transition on TBRL initiates data transfer to
the transmitter register. If busy, transfer is auto-
matically delayed so that the two characters are
transmitted end to end.
A high level on TRANSMITTER REGISTER EMP-
TY indicates completed transmission of a charac-
ter including stop bits.
Character data, start data and stop bits appear se-
rially at the TRANSMITTER REGISTER OUTPUT.
Character data is loaded into the TRANSMITTER
BUFFER REGISTER via inputs TBR1-TBR8. For
character formats less than 8 bits the TBR8, 7 and
6 inputs are ignored corresponding to their pro-
grammed word length.
See Pin 26-TBR1.
See Pin 26-TBR1.
See Pin 26-TBR1.
See Pin 26-TBR1.
See Pin 26-TBR1.
See Pin 26-TBR1.
See Pin 26-TBR1.
A high level on CONTROL REGISTER LOAD
loads the control register with the control word. The
control word is latched on the falling edge of CRL.
CRL may be tied high.
A high level on PARITY INHIBIT inhibits parity gen-
eration, parity checking and forces PE output low.
A high level on STOP BIT SELECT selects 1.5
stop bits for 5 character format and 2 stop bits for
other lengths.
These inputs program the CHARACTER
LENGTH SELECTED (CLS1 low CLS2 low 5 bits)
(CLS1 high CLS2 low 6 bits) (CLS1 low CLS2
high 7 bits) (CLS1 high CLS2 high 8 bits.)
See Pin 37-CLS2.
When PI is low, a high level on EVEN PARITY
ENABLE generates and checks even parity. A low
level selects odd parity.
The TRANSMITTER REGISTER CLOCK is 16X
the transmit data rate.
5
O
RBR8
6
7
8
9
10
11
12
13
O
O
O
O
O
O
O
O
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1
PE
14
15
O
O
FE
OE
16
I
SFD
17
18
19
I
I
O
RRC
DRR
DR
35
36
I
I
PI
SBS
20
21
I
I
RRI
MR
37
I
CLS2
38
39
I
I
CLS1
EPE
40
I
TRC
†
A 0.1µF decoupling capacitor from the V
CC
pin to the GND is rec-
ommended.
20
21
19
22
18
23
17
24
16
25
15
26
14
27
13
28
12
29
HD-6402
5-102
11
30
10
31
9
32
8
33
7
34
6
35
5
36
4
37
3
38
2
39
1
40
HD-6402
Transmitter Operation
The transmitter section accepts parallel data, formats the data
and transmits the data in serial form on the Transmitter Regis-
ter Output (TRO) terminal (See serial data format). Data is
loaded from the inputs TBR1-TBR8 into the Transmitter Buffer
Register by applying a logic low on the Transmitter Buffer
Register Load (TBRL) input (A). Valid data must be present at
least t
set
prior to and t
hold
following the rising edge of TBRL. If
words less than 8 bits are used, only the least significant bits
are transmitted. The character is right justified, so the least
significant bit corresponds to TBR1 (B).
The rising edge of TBRL clears Transmitter Buffer Register
Empty (TBRE). 0 to 1 Clock cycles later, data is transferred
to the transmitter register, the Transmitter Register Empty
(TRE) pin goes to a low state, TBRE is set high and serial
data information is transmitted. The output data is clocked by
Transmitter Register Clock (TRC) at a clock rate 16 times the
data rate. A second low level pulse on TBRL loads data into
the Transmitter Buffer Register (C). Data transfer to the
transmitter register is delayed until transmission of the cur-
rent data is complete (D). Data is automatically transferred to
the transmitter register and transmission of that character
begins one clock cycle later.
1
TBRL
TBRE
0 TO 1 CLOCK
TRE
TRO
A
B
C
DATA
D
END OF LAST STOP BIT
1/2 CLOCK
FIGURE 1. TRANSMITTER TIMING (NOT TO SCALE)
Receiver Operation
Data is received in serial form at the Receiver Register Input
(RRI). When no data is being received, RRI must remain
high. The data is clocked through the Receiver Register
Clock (RRC). The clock rate is 16 times the data rate. A low
level on Data Received Reset (DRR) clears the Data
Receiver (DR) line (A). During the first stop bit data is trans-
ferred from the Receiver Register to the Receiver Buffer
Register (RBR) (B). If the word is less than 8 bits, the
unused most significant bits will be a logic low. The output
character is right justified to the least significant bit RBR1. A
logic high on Overrun Error (OE) indicates overruns. An
overrun occurs when DR has not been cleared before the
present character was transferred to the RBR. One clock
cycle later DR is reset to a logic high, and Framing Error
(FE) is evaluated (C). A logic high on FE indicates an invalid
stop bit was received, a framing error. A logic high on Parity
Error (PE) indicates a parity error.
BEGINNING OF FIRST STOP BIT
RRI
7 1/2 CLOCK CYCLES
RBR1-8, OE, PE
DRR
DR
FE
1 CLOCK CYCLE
A
B
C
FIGURE 2. RECEIVER TIMING (NOT TO SCALE)
START BIT
5-8 DATA BITS
1, 11/2 OR 2 STOP BITS
LSB
MSB
†
PARITY
†
IF ENABLED
FIGURE 3. SERIAL DATA FORMAT
5-103
HD-6402
Start Bit Detection
The receiver uses a 16X clock timing. The start bit could have
occurred as much as one clock cycle before it was detected,
as indicated by the shaded portion (A). The center of the start
bit is defined as clock count 7 1/2. If the receiver clock is a
symmetrical square wave, the center of the start bit will be
located within
±1/2
clock cycle,
±1/32
bit or 3.125% giving a
receiver margin of 46.875%. The receiver begins searching
for the next start bit at the center of the first stop bit.
CLOCK
RRI INPUT
A
START
71/2 CLOCK CYCLES
81/2 CLOCK CYCLES
COUNT 71/2 DEFINED
CENTER OF START BIT
FIGURE 4.
Interfacing with the HD-6402
TRANSMITTER
TBR1
TBR8
CONTROL
DIGITAL
SYSTEM
HD-6402
CONTROL
RB1
RRI
RS232
RECEIVER
RS232
DRIVER
TRO
RS232
DRIVER
RS232
RECEIVER
RECEIVER
RB1
RRI
RB8
CONTROL
HD-6402
CONTROL
TRO
TBR1
DIGITAL
SYSTEM
RB8
RECEIVER
TBR8
TRANSMITTER
FIGURE 5. TYPICAL SERIAL DATA LINK
5-104
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