Cascading Multiple HSP45256 Correlators
Technical Brief
May 1998
TB306.1
When multiple correlators are cascaded for longer reference
data sets, the Programmable Delay is used to adjust the tim-
ing between chips so that they can be connected with no
external hardware. Figure 1 shows the portions of two corre-
lators that would be active when two 45256's are set up to
perform a 1 bit, 512 tap correlation. In this case, DOUT7 of
one correlator is connected to DIN7 of the next one;
CASOUT0-12 of the first part are connected to CASIN0-12
of the second one. (See the HSP45256 Data Sheet). Figure
2 shows the relevant portions of two Correlators which are
cascaded together; in this example, each is configured as
1x256. In the interest of clarity, the only portions shown are
the final stage of the first correlator and the first stage of the
second one. The data sample number at each stage for a
given clock cycle is shown in the boxed in numbers. Note
that the Programmable Delay of the first part is set to a delay
of one (the minimum possible) and the second part is set to
a delay of two. This assures that the proper samples are
added in the Cascade Summer.
HSP45256
INPUT DATA
DIN0-7
DOUT0-7
CASOUT0-12
REFERENCE DATA
DREF0-7
DCONT0-7
FROM MICROPROCESSOR:
DATA BUS
A0-2
AUXOUT0-7
CLOAD
DIN0-7
HSP45256
CASIN0-12
DREF0-7
DCONT0-7
CASOUT0-12
A0-2
CLOAD
ADDRESS BITS 0-2
ADDRESS BITS 3-N
WE
A
EN
DECODE
FIGURE 1. CIRCUIT BLOCK DIAGRAM
1
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Technical Brief 306
DATA OUT
DIN7
DO7
32 TAP
CORRELATOR STAGE
R
E
G
DOUT7
1026
WEIGHT
AND
SUM
R
E
G
PROGRAMMABLE
DELAY
DELAY = 2
1028
1029
R
E
G
CASCADE
SUMMER
CASOUT0-12
. . .
1024
R CO7 1025
E
G CORRELATION
SCORE OUT
+
+
1028
1024
CORRELATOR #2
DIN7
DO7
32 TAP
CORRELATOR STAGE
1023
R
E
G
R CO7
E
G
1024
WEIGHT
AND
SUM
CORRELATOR #1
1025
R
E
G
PROGRAMMABLE
DELAY
DELAY = 1
"0"
1026
CASIN0-12
R
E
G
CASOUT0-12
1027
CASCADE
REGISTER
. . .
1023
+
FIGURE 2. CASCADED CORRELATORS SHOWING RELATIVE CLOCK CYCLES
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