Data sheet acquired from Harris Semiconductor
SCHS146F
CD74HC137, CD74HCT137,
CD54HC237, CD74HC237,
CD74HCT237
High-Speed CMOS Logic, 3- to 8-Line
Decoder/Demultiplexer with Address Latches
Both circuits have three binary select inputs (A0, A1 and A2)
that can be latched by an active High Latch Enable (LE)
signal to isolate the outputs from select-input changes. A
“Low” LE makes the output transparent to the input and the
circuit functions as a one-of-eight decoder. Two Output
Enable inputs (OE
1
and OE
0
) are provided to simplify
cascading
and
to
facilitate
demultiplexing.
The
demultiplexing function is accomplished by using the A
0
, A
1
,
A
2
inputs to select the desired output and using one of the
other Output Enable inputs as the data input while holding
the other Output Enable input in its active state. In the
CD74HC137 and CD74HCT137 the selected output is a
“Low”; in the ’HC237 and CD74HCT237 the selected output is
a “High”.
March 1998 - Revised October 2003
Features
[ /Title
(CD74
HC137
,
CD74
HCT13
7,
CD74
HC237
,
CD74
HCT23
7)
/Sub-
ject
(High
Speed
• Select One of Eight Data Outputs
- Active Low for CD74HC137 and CD74HCT137
- Active High for ’HC237 and CD74HCT237
• l/O Port or Memory Selector
• Two Enable Inputs to Simplify Cascading
• Typical Propagation Delay of 13ns at V
CC
= 5V,
15pF, T
A
= 25
o
C (CD74HC237)
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30%, of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤
1µA at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC237F3A
CD74HC137E
CD74HC137PW
CD74HC137PWR
CD74HC137PWT
CD74HC237E
CD74HC237M
CD74HC237MT
CD74HC237M96
CD74HC237NSR
CD74HC237PW
CD74HC237PWR
CD74HC237PWT
CD74HCT137E
CD74HCT137MT
CD74HCT137M96
CD74HCT237E
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
Description
The
CD74HC137,
CD74HCT137,
’HC237,
and
CD74HCT237 are high speed silicon gate CMOS decoders
well suited to memory address decoding or data routing
applications. Both circuits feature low power consumption
usually associated with CMOS circuitry, yet have speeds
comparable to low power Schottky TTL logic.
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
2003, Texas Instruments Incorporated
1
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237
Pinout
CD54HC237 (CERDIP)
CD74HC137 (PDIP, TSSOP)
CD74HCT137 (PDIP, SOIC)
CD74HC237 (PDIP, SOIC, SOP, TSSOP)
CD74HCT237 (PDIP)
TOP VIEW
A
0
1
A
1
2
A
3
3
LE 4
OE
1
5
OE
0
6
Y
7
7
GND 8
16 V
CC
15 Y
0
14 Y
1
13 Y
2
12 Y
3
11 Y
4
10 Y
5
9 Y
6
OE
1
OE
0
5
6
GND = 8
V
CC
= 16
10
9
7
LE
Functional Diagram
1
2
3
4
3-BIT
LATCH
HC/HCT HC/HCT
237
137
15
Y
0
Y
0
14
1 OF 8
DECODER 13
12
11
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
A
0
A
1
A
2
’HC137, ’HCT137 TRUTH TABLE
INPUTS
LE
X
X
L
L
L
L
L
L
L
L
H
OE
0
X
L
H
H
H
H
H
H
H
H
H
OE
1
H
X
L
L
L
L
L
L
L
L
L
A
2
X
X
L
L
L
L
H
H
H
H
X
A
1
X
X
L
L
H
H
L
L
H
H
X
A
0
X
X
L
H
L
H
L
H
L
H
X
Y
0
H
H
L
H
H
H
H
H
H
H
Y
1
H
H
H
L
H
H
H
H
H
H
Y
2
H
H
H
H
L
H
H
H
H
H
OUTPUTS
Y
3
H
H
H
H
H
L
H
H
H
H
Y
4
H
H
H
H
H
H
L
H
H
H
Y
5
H
H
H
H
H
H
H
L
H
H
Y
6
H
H
H
H
H
H
H
H
L
H
Y
7
H
H
H
H
H
H
H
H
H
L
Depends upon the address previously applied while LE was at a logic low.
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
’HC237, ’HCT237 TRUTH TABLE
INPUTS
LE
X
X
L
L
L
L
L
L
L
L
H
OE
0
X
L
H
H
H
H
H
H
H
H
H
OE
1
H
X
L
L
L
L
L
L
L
L
L
A
2
X
X
L
L
L
L
H
H
H
H
X
A
1
X
X
L
L
H
H
L
L
H
H
X
A
0
X
X
L
H
L
H
L
H
L
H
X
Y
0
L
L
H
L
L
L
L
L
L
L
Y
1
L
L
L
H
L
L
L
L
L
L
Y
2
L
L
L
L
H
L
L
L
L
L
OUTPUTS
Y
3
L
L
L
L
L
H
L
L
L
L
Y
4
L
L
L
L
L
L
H
L
L
L
Y
5
L
L
L
L
L
L
L
H
L
L
Y
6
L
L
L
L
L
L
L
L
H
L
Y
7
L
L
L
L
L
L
L
L
L
H
Depends upon the address previously applied while LE was at a logic low.
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
2
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237
Functional Block Diagram
A
0
LE
1
A
0
p
n
LE
LE
p
n
LE
A
1
2
A
1
A1 LATCH
A
0
11
Y
4
10
3
A
2
A2 LATCH
A
2
A
2
9
Y
6
LE
4
LE
LE
7
Y
7
Y
5
12
Y
3
13
Y
2
A
0
15
Y
0
14
Y
1
5
OE
1
6
OE
0
3
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237
Absolute Maximum Ratings
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Package Thermal Impedance,
θ
JA
(see Note 1):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
o
C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
o
C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
o
C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108
o
C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
4.5
6
Low Level Input
Voltage
V
IL
-
-
2
4.5
6
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
I
V
CC
or
GND
V
OL
V
IH
or V
IL
V
OH
V
IH
or V
IL
-0.02
-0.02
-0.02
-
-4
-5.2
0.02
0.02
0.02
-
4
5.2
-
2
4.5
6
-
4.5
6
2
4.5
6
-
4.5
6
6
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.98
5.48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.26
0.26
±0.1
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.84
5.34
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.33
0.33
±1
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.7
5.2
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.4
0.4
±1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
SYMBOL
V
I
(V)
I
O
(mA)
V
CC
(V)
25
o
C
MIN
TYP
MAX
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
MAX
MIN
MAX
UNITS
4
CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Quiescent Device
Current
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
I
I
I
CC
∆I
CC
(Note 2)
V
CC
and
GND
V
CC
or
GND
V
CC
-2.1
V
OL
V
IH
or V
IL
V
IH
V
IL
V
OH
-
-
V
IH
or V
IL
-
-
-0.02
4.5 to
5.5
4.5 to
5.5
4.5
2
-
4.4
-
-
-
-
0.8
-
2
-
4.4
-
0.8
-
2
-
4.4
-
0.8
-
V
V
V
SYMBOL
I
CC
V
I
(V)
V
CC
or
GND
I
O
(mA)
0
25
o
C
MIN
-
TYP
-
MAX
8
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
-
MAX
80
MIN
-
MAX
160
UNITS
µA
V
CC
(V)
6
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
0
0
-
5.5
5.5
4.5 to
5.5
-
-
-
-
-
100
±0.1
8
360
-
-
-
±1
80
450
-
-
-
±1
160
490
µA
µA
µA
HCT Input Loading Table
INPUT
All
UNIT LOADS
1.5
NOTE: Unit Load is
∆I
CC
limit specified in DC Electrical Table, e.g.,
360µA max at 25
o
C.
Prerequisite For Switching Specifications
PARAMETER
HC TYPES
A
n
to LE Setup Time
SYMBOL
t
SU
V
CC
(V)
2
4.5
6
A
n
to LE Hold Time
t
H
2
4.5
6
25
o
C
MIN
50
10
9
30
6
5
TYP
-
-
-
-
-
-
MAX
-
-
-
-
-
-
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
65
13
11
40
8
7
MAX
-
-
-
-
-
-
MIN
75
15
13
45
9
8
MAX
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
5
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