74ACT563 Octal Latch with 3-STATE Outputs
April 2007
74ACT563
Octal Latch with 3-STATE Outputs
Features
■
I
CC
and I
OZ
reduced by 50%
■
Inputs and outputs on opposite sides of package allow
■
■
■
■
tm
General Description
The ACT563 is a high-speed octal latch with buffered
common Latch Enable (LE) and buffered common Out-
put Enable (OE) inputs.
The ACT563 device is functionally identical to the
ACT573, but with inverted outputs.
easy interface with microprocessors
Useful as input or output port for microprocessors
Functionally identical to ACT573 but with inverted
outputs
Outputs source/sink 24mA
ACT563 has TTL-compatible inputs
Ordering Information
Order
Number
74ACT563SC
Package
Number
M20B
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide Body
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Description
FACT™ is a trademark of Fairchild Semiconductor Corporation.
©1988 Fairchild Semiconductor Corporation
74ACT563 Rev. 1.2
www.fairchildsemi.com
74ACT563 Octal Latch with 3-STATE Outputs
Functional Description
The ACT563 contains eight D-type latches with
3-STATE complementary outputs. When the Latch
Enable (LE) input is HIGH, data on the D
n
inputs enters
the latches. In this condition the latches are transparent,
i.e., a latch output will change state each time its D input
changes. When LE is LOW the latches store the informa-
tion that was present on the D inputs at setup time pre-
ceding the HIGH-to-LOW transition of LE. The 3-STATE
buffers are controlled by the Output Enable (OE) input.
When OE is LOW, the buffers are in the bi-state mode.
When OE is HIGH the buffers are in the high impedance
mode but that does not interfere with entering new data
into the latches.
Function Table
Inputs
OE LE
H
H
H
H
L
L
L
X
H
H
L
H
H
L
Internal
D
X
L
H
X
L
H
X
Output
O
Z
Z
Z
Z
H
L
NC
Q
X
H
L
NC
H
L
NC
Function
High-Z
High-Z
High-Z
Latched
Transparent
Transparent
Latched
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
NC
=
No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Figure 1.
©1988 Fairchild Semiconductor Corporation
74ACT563 Rev. 1.2
www.fairchildsemi.com
2
74ACT563 Octal Latch with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5V
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±50mA
±50mA
–65°C to +150°C
140°C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
V
O
T
A
∆
V /
∆
t
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Minimum Input Edge Rate:
Parameter
Rating
4.5V to 5.5V
0V to V
CC
0V to V
CC
–40°C to +85°C
125mV/ns
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1988 Fairchild Semiconductor Corporation
74ACT563 Rev. 1.2
www.fairchildsemi.com
3
74ACT563 Octal Latch with 3-STATE Outputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
T
A
=
+25°C
Conditions
V
OUT
=
0.1V or
V
CC
– 0.1V
V
OUT
=
0.1V or
V
CC
– 0.1V
I
OUT
=
–50µA
V
IN
=
V
IL
or V
IH
:
T
A
=
–40°C to +85°C
Guaranteed Limits
Units
V
V
V
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
±2.5
1.5
75
–75
µA
µA
mA
mA
mA
µA
V
Typ.
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.001
0.001
0.1
0.1
0.36
0.36
±0.1
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
I
OH
=
–24mA
I
OH
=
–24mA
(1)
I
OUT
=
50µA
V
IN
=
V
IL
or V
IH
:
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Maximum 3-STATE
Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current
(2)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
5.5
5.5
I
OL
=
24mA
I
OL
=
24mA
(1)
V
I
=
V
CC
, GND
V
I
= V
IL
, V
IH
;
V
O
= V
CC
, GND
V
I
=
V
CC
– 2.1V
V
OLD
=
1.65V Max.
V
OHD
=
3.85V Min.
V
IN
=
V
CC
or GND
0.6
±0.25
4.0
40.0
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74ACT563 Rev. 1.2
www.fairchildsemi.com
4
74ACT563 Octal Latch with 3-STATE Outputs
AC Electrical Characteristics
T
A
=
+25°C,
C
L
=
50pF
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
T
A
=
–40°C to +85°C,
C
L
=
50pF
Min.
2.5
2.5
2.5
2.0
2.0
2.0
2.5
1.0
Parameter
Propagation Delay,
D
n
to O
n
Propagation Delay,
D
n
to O
n
Propagation Delay,
LE to O
n
Propagation Delay,
LE to O
n
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
V
CC
(V)
(3)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
Min.
3.0
3.0
3.0
2.5
2.5
2.0
3.5
2.0
Typ.
7.0
6.0
6.5
5.5
5.5
5.5
6.5
4.5
Max.
11.5
10.0
10.5
9.5
9.0
8.5
10.5
8.0
Max.
12.5
11.0
11.5
10.5
10.0
9.5
11.5
8.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
Note:
3. Voltage range 5.0 is 5.0V ± 0.5V.
AC Operating Requirements
T
A
=
+25°C,
C
L
=
50pF
Symbol
t
S
t
H
t
W
T
A
=
–40°C to +85°C,
C
L
=
50pF
Units
ns
ns
ns
4.5
0
3.0
Parameter
Setup Time, HIGH or LOW,
D
n
to LE
Hold Time, HIGH or LOW,
D
n
to LE
LE Pulse Width, HIGH
V
CC
(V)
(4)
5.0
5.0
5.0
Typ.
1.5
–2.0
2.0
Guaranteed Minimum
4.0
0
3.0
Note:
4. Voltage range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Conditions
V
CC
=
OPEN
V
CC
=
5.0V
Typ.
4.5
50.0
Units
pF
pF
©1988 Fairchild Semiconductor Corporation
74ACT563 Rev. 1.2
www.fairchildsemi.com
5
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