74LVC16374A-Q100;
74LVCH16374A-Q100
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
Rev. 1 — 28 January 2013
Product data sheet
1. General description
The 74LVC16374A-Q100 and 74LVCH16374A-Q100 are 16-bit edge-triggered flip-flops
featuring separate D-type inputs with bus hold (74LVCH16374A-Q100 only) for each
flip-flop and 3-state outputs for bus-oriented applications. It consists of two sections of
eight positive edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE)
are provided for each octal. The flip-flops store the state of their individual D-inputs that
meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition.
The flip-flops store the state of their individual D-inputs that meet the set-up and hold time
requirements on the LOW-to-HIGH clock (CP) transition.
When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin
nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE
does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V
devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow
the use of these devices in mixed 3.3 V and 5 V applications. Bus hold on data inputs
eliminates the need for external pull-up resistors to hold unused inputs.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Low inductance multiple supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16374A-Q100 only)
High-impedance outputs when V
CC
= 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
NXP Semiconductors
74LVC16374A-Q100; 74LVCH16374A-Q100
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74LVC16374ADGG-Q100
74LVCH16374ADGG-Q100
40 C
to +125
C
Name
TSSOP48
Description
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT362-1
Type number
4. Functional diagram
1
1OE
48
1CP
24
2OE
25
2CP
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1CP
48
2CP
25
001aaa253
EN1
C3
EN2
C4
3D
1
2
3
5
6
8
9
11
12
4D
2
13
14
16
17
19
20
22
23
001aaa254
1
1OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
24
2OE
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC_LVCH16374A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 28 January 2013
2 of 17
NXP Semiconductors
74LVC16374A-Q100; 74LVCH16374A-Q100
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
1D0
D
CP
FF1
Q
1Q0
2D0
D
CP
FF2
Q
2Q0
1CP
1OE
2CP
2OE
to 7 other channels
to 7 other channels
001aaa255
Fig 3.
Logic diagram
V
CC
data input
to internal circuit
mna705
Fig 4.
Bus hold circuit
74LVC_LVCH16374A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 28 January 2013
3 of 17
NXP Semiconductors
74LVC16374A-Q100; 74LVCH16374A-Q100
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
5. Pinning information
5.1 Pinning
/9&$4
/9&+$4
2(
4
4
*1'
4
4
9
&&
4
4
&3
'
'
*1'
'
'
9
&&
'
'
*1'
'
'
'
'
*1'
'
'
9
&&
'
'
*1'
'
'
&3
DDD
*1'
4
4
4
4
*1'
4
4
9
&&
4
4
*1'
4
4
2(
Fig 5.
Pin configuration SOT362-1 (TSSOP48)
74LVC_LVCH16374A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 28 January 2013
4 of 17
NXP Semiconductors
74LVC16374A-Q100; 74LVCH16374A-Q100
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
5.2 Pin description
Table 2.
Symbol
1OE, 2OE
GND
V
CC
1Q0 to 1Q7
2Q0 to 2Q7
1D0 to 1D7
2D0 to 2D7
1CP, 2CP
Pin description
Pin
1, 24
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
48, 25
Description
output enable input (active LOW)
ground (0 V)
supply voltage
data output
data output
data input
data input
clock input
6. Functional description
Table 3.
Function selection
[1]
Input
nOE
Load and read register
Load register and disable outputs
L
L
H
H
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;
= LOW-to-HIGH transition;
Z = high-impedance OFF-state.
Operating mode
Internal flip-flop
nCP
nDn
l
h
l
h
L
H
L
H
Output nQ0 to nQ7
L
H
Z
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
V
O
> V
CC
or V
O
< 0 V
output HIGH-or LOW-state
output 3-state
V
O
= 0 V to V
CC
[2]
[2]
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
0.5
0.5
-
-
100
65
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
+150
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
74LVC_LVCH16374A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 28 January 2013
5 of 17
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