74LVC16245A-Q100;
74LVCH16245A-Q100
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
Rev. 1 — 20 November 2012
Product data sheet
1. General description
The 74LVC16245A-Q100; 74LVCH16245A-Q100 are 16-bit transceivers featuring
non-inverting 3-state bus compatible outputs in both send and receive directions. The
device features two output-enable (nOE) inputs for easy cascading and two send/receive
(nDIR) inputs for direction control. nOE controls the outputs so that the buses are
effectively isolated. This device can be used as two 8-bit transceivers or one 16-bit
transceiver. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to
5.5 V can be applied to the outputs. These features allow the use of these devices in
mixed 3.3 V and 5 V applications.
The 74LVCH16245A-Q100 bus hold on data inputs eliminates the need for external
pull-up resistors to hold unused inputs.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
MULTIBYTE flow-through standard pinout architecture
Low inductance multiple power and ground pins for minimum noise and ground
bounce
Direct interface with TTL levels
High-impedance when V
CC
= 0 V
All data inputs have bus hold (74LVCH16245A-Q100 only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
NXP Semiconductors
74LVC16245A-Q100; 74LVCH16245A-Q100
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
3. Ordering information
Table 1.
Ordering information
Temperature range Package
Name
74LVC16245ADGG-Q100
74LVCH16245ADGG-Q100
74LVC16245AEV-Q100
74LVCH16245AEV-Q100
40 C
to +125
C
VFBGA56
40 C
to +125
C
TSSOP48
Description
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
plastic very thin fine-pitch ball grid array
package; 56 balls; body 4.5
7
0.65 mm
Version
SOT362-1
SOT702-1
Type number
4. Functional diagram
1DIR
1OE
1A0
1B0
1A1
1B1
1A2
1B2
1A3
1B3
1A4
1B4
1A5
1B5
1A6
1B6
1A7
1B7
2DIR
2OE
2A0
2B0
2A1
2B1
2A2
2B2
2A3
2B3
2A4
2B4
2A5
2B5
2A6
2B6
2A7
2B7
001aaa789
Fig 1.
Logic symbol
74LVC_LVCH16245A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 November 2012
2 of 17
NXP Semiconductors
74LVC16245A-Q100; 74LVCH16245A-Q100
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
1OE
1DIR
2OE
2DIR
G3
3EN1[BA]
3EN2[AB]
G6
6EN1[BA]
6EN2[AB]
1A0
1
2
1B0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
4
5
2A1
2A2
2A3
2A4
2A5
2A6
2A7
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
001aaa790
Fig 2.
IEC logic symbol
V
CC
data input
to internal circuit
mna705
Fig 3.
Bus hold circuit
74LVC_LVCH16245A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 November 2012
3 of 17
NXP Semiconductors
74LVC16245A-Q100; 74LVCH16245A-Q100
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
5. Pinning information
5.1 Pinning
/9&$4
/9&+$4
',5
%
%
*1'
%
%
9
&&
%
%
2(
$
$
*1'
$
$
9
&&
$
$
*1'
$
$
$
$
*1'
$
$
9
&&
$
$
*1'
$
$
2(
DDD
*1'
%
%
%
%
*1'
%
%
9
&&
%
%
*1'
%
%
',5
/9&$4
/9&+$B4
EDOO $
LQGH[ DUHD
$
%
&
'
(
)
*
+
-
.
DDD
7UDQVSDUHQW WRS YLHZ
Fig 4.
Pin configuration SOT362-1 (TSSOP48)
Fig 5.
Pin configuration SOT702-1 (VFBGA56)
74LVC_LVCH16245A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 November 2012
4 of 17
NXP Semiconductors
74LVC16245A-Q100; 74LVCH16245A-Q100
16-bit bus transceiver with direction pin; 5 V tolerant; 3-state
5.2 Pin description
Table 2.
Symbol
1DIR, 2DIR
1B0 to 1B7
2B0 to 2B7
GND
V
CC
1OE, 2OE
1A0 to 1A7
2A0 to 2A7
n.c.
Pin description
Pin
SOT362-1
1, 24
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20,
22, 23
SOT702-1
A1, K1
B2, B1, C2, C1, D2, D1, E2, E1
F1, F2, G1, G2, H1, H2, J1, J2
direction control input
data input/output
data input/output
ground (0 V)
supply voltage
output enable input (active LOW)
data input/output
data input/output
not connected
Description
4, 10, 15, 21, 28, 34, 39, B3, B4, D3, D4, G3, G4, J3, J4
45
7, 18, 31, 42
48, 25
47, 46, 44, 43, 41, 40,
38, 37
36, 35, 33, 32, 30, 29,
27, 26
-
C3, C4, H3, H4
A6, K6
B5, B6, C5, C6, D5, D6, E5, E6
F6, F5, G6, G5, H6, H5, J6, J5
A2, A3, A4, A5, K2, K3, K4, K5
6. Functional description
Table 3.
Inputs
nOE
L
L
H
[1]
Function table
[1]
Outputs
nDIR
L
H
X
nAn
nAn = nBn
inputs
Z
nBn
inputs
nBn = nAn
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
74LVC_LVCH16245A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 November 2012
5 of 17
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
