Agilent HCPL-0738
High Speed CMOS Optocoupler
Data Sheet
Features
• 15 ns typical pulse width
distortion
• 40 ns maximum prop. delay skew
Description
The HCPL-0738 is a dual-channel
15 MBd CMOS optocoupler in
SOIC-8 package. The HCPL-0738
optocoupler utilizes the latest CMOS
IC technology to achieve out-
standing performance with very low
power consumption. Basic building
blocks of HCPL-0738 are high
speed LEDs and CMOS detector ICs.
• 20 ns typical prop. delay
Agilent also offers the same
performance in the single channel
version, HCPL-0708. Each
detector incorporates an
integrated photodiode, a high
speed transimpedance amplifier,
and a voltage comparator with an
output driver.
• High speed: 15 MBd
• + 5 V CMOS compatibility
• 10 kV/µS minimum common mode
rejection
• –40 to 100˚C temperature range
• Safety and regulatory approvals
– UL recognized (3750 V rms for
1 minute per UL 1577)
– CSA component acceptance
notice #5.
– IEC/EN/DIN EN 60747-5-2
approved for HCPL-0738
Option 060
Applications
• PDP (plasma display panel)
• Digital field bus isolation:
DeviceNet, SDS, Profibus
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
• DC/DC converter
Functional Diagram
Truth Table
ANODE 1
1
8
V
DD
CATHODE 1
2
7
V
O
1
LED
OFF
ON
V
O
, Output
H
L
CATHODE 2
3
6
V
O
2
Note: A 0.1
µF
bypass capacitor must be
connected between pins 5 and 8.
ANODE 2
4
5
GND
CAUTION:
It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.
Selection Guide
Small Outline SO-8
HCPL-0738
Ordering Information
Specify Part Number followed by
Option Number (if desired).
Example
HCPL-0738 -060 = IEC/EN/DIN
EN 60747-5-2 Option
HCPL-0738 -500 = Tape and
Reel Packaging Option
HCPL-0738-XXXE = Lead Free
Option
No Option Code contains 100
units per tube. Option 500
contains 1500 units per reel.
Option data sheets available.
Contact Agilent Technologies
sales representative or authorized
distributor.
Package Outline Drawing
HCPL-0738 Outline Drawing (Small Outline SO-8 Package)
LAND PATTERN RECOMMENDATION
8
7
6
XXX
YWW
5
5.994 ± 0.203
(0.236 ± 0.008)
TYPE NUMBER
(LAST 3 DIGITS)
3.937 ± 0.127
(0.155 ± 0.005)
7.49 (0.295)
PIN 1
ONE
0.405 ± 0.076
(0.015 ± 0.003)
2
3
4
1.270 BSC
(0.050)
DATE CODE
1.9 (0.075)
0.64 (0.025)
7°
45° x 0.432
(0.017)
*5.080 ± 0.127
(0.205 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005)
1.524
(0.060)
0 - 7°
0.228 ± 0.025
(0.009 ± 0.001)
0.202 ± 0.102
(0.008 ± 0.004)
0.305
MIN.
(0.012)
*TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
DIMENSIONS IN MILLIMETERS AND (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
2
Solder Reflow Temperature Profile
300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
2.5°C ± 0.5°C/SEC.
160°C
150°C
140°C
3°C + 1°C/–0.5°C
30
SEC.
30
SEC.
SOLDERING
TIME
200°C
TEMPERATURE (°C)
200
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
200
250
TIME (SECONDS)
Recommended Pb-Free IR Profile
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
t
p
T
p
T
L
260 +0/-5 °C
217 °C
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
TEMPERATURE
T
smax
T
smin
RAMP-DOWN
6 °C/SEC. MAX.
t
s
PREHEAT
60 to 180 SEC.
25
t 25 °C to PEAK
t
L
60 to 150 SEC.
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
T
smax
= 200 °C, T
smin
= 150 °C
3
Regulatory Information
The HCPL-0738 has been
approved by the following
organizations:
UL
Recognized under UL 1577,
component recognition program,
File E55361.
CSA
Approved under CSA Component
Acceptance Notice #5, File
CA88324.
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01
(Option 060 only)
Insulation and Safety Related Specifications (approval pending)
Parameter
Minimum External Air Gap
(Clearance)
Minimum External Tracking
(Creepage)
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
Isolation Group
All Agilent data sheets report the
creepage and clearance inherent
to the optocoupler component
itself. These dimensions are
needed as a starting point for the
equipment designer when deter-
mining the circuit insulation re-
quirements. However, once
mounted on a printed circuit
Absolute Maximum Ratings
Parameter
Storage Temperature
Ambient Operating Temperature
Supply Voltage
Output Voltage
Average Forward Input Current
Average Output Current
Lead Solder Temperature
Solder Reflow Temperature Profile
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Supply Voltages
Input Current (ON)
4
Symbol
T
A
V
DD
I
F
Minimum
–40
4.5
10
Maximum
100
5.5
16
Units
˚C
V
mA
Symbol
Minimum
Maximum
T
S
–55
125
T
A
–40
100
V
DD
0
6.0
V
O
–0.5
V
DD
+ 0.5
I
F
—
20
I
O
—
2
260˚C for 10 seconds, 1.6 mm below seating plane
See Solder Reflow Thermal Profile section
Units
˚C
˚C
Volts
Volts
mA
mA
CTI
Symbol
L(I01)
L(I02)
Value
4.9
4.8
0.08
≥
175
IIIa
Units
mm
mm
mm
Volts
Conditions
Measured from input terminals to output terminals,
shortest distance through air.
Measured from input terminals to output terminals,
shortest distance path along body.
Insulation thickness between emitter and detector; also
known as distance through insulation.
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
are recommended techniques
such as grooves and ribs which
may be used on a printed circuit
board to achieve desired creep-
age and clearances. Creepage and
clearance distances will also
change depending on factors
such as pollution degree and
insulation level.
board, minimum creepage and
clearance requirements must be
met as specified for individual
equipment standards. For creep-
age, the shortest distance path
along the surface of a printed
circuit board between the solder
fillets of the input and output
leads must be considered. There
Electrical Specifications
Over recommended temperature (T
A
= –40˚C to +100˚C) and 4.5 V
≤
V
DD
≤
5.5 V.
All typical specifications are at T
A
= 25˚C, V
DD
= +5 V.
Parameter
Input Forward Voltage
Input Reverse Breakdown
Voltage
Logic High Output Voltage
Logic Low Output Voltage
Input Threshold Current
Logic Low Output Supply
Current
Logic High Output Supply
Current
Symbol
V
F
BV
R
V
OH
V
OL
I
TH
I
DDL
I
DDH
Min.
1.3
5
4.0
Typ.
1.5
Max.
1.8
Units
V
V
V
0.1
8.2
18.0
15.0
V
mA
mA
mA
Test Conditions
I
F
= 12 mA
I
R
= 10
µA
I
F
= 0, I
O
= –20
µA
I
F
= 12 mA, I
O
= 20
µA
I
OL
= 20
µA
I
F
= 12 mA
I
F
= 0 mA
2
4
3
Fig.
1
Notes
5
0.01
4.5
10
8
Switching Specifications
Over recommended temperature (T
A
= –40˚C to +100˚C) and 4.5 V
≤
V
DD
≤
5.5 V.
All typical specifications are at T
A
= 25˚C, V
DD
= +5 V.
Parameter
Propagation Delay Time
to Logic Low Output
Propagation Delay Time
to Logic High Output
Pulse Width
Pulse Width Distortion
Propagation Delay Skew
Output Rise Time
(10% – 90%)
Output Fall Time
(90% – 10%)
Common Mode Transient
Immunity at Logic High Output
Common Mode Transient
Immunity at Logic Low Output
Symbol
t
PHL
t
PLH
PW
|PWD|
t
PSK
t
R
t
F
|CM
H
|
|CM
L
|
10
10
20
25
15
15
Min.
20
11
100
0
Typ.
35
20
Max.
60
60
Units
ns
ns
ns
ns
ns
ns
ns
kV/µS
kV/µS
Test Conditions
I
F
= 12 mA, C
L
= 15 pF
CMOS Signal Levels
I
F
= 12 mA, C
L
= 15 pF
CMOS Signal Levels
I
F
= 12 mA, C
L
= 15 pF
CMOS Signal Levels
I
F
= 12 mA, C
L
= 15 pF
CMOS Signal Levels
I
F
= 0 mA, C
L
= 15 pF
CMOS Signal Levels
I
F
= 12 mA, C
L
= 15 pF
CMOS Signal Levels
V
CM
= 1000 V, T
A
= 25˚C,
I
F
= 0 mA
V
CM
= 1000 V, T
A
= 25˚C,
I
F
= 12 mA
Fig.
5
5
Notes
1
1
15
30
40
5
2
3
4
5
5
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