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74F350 4-Bit Shifter with 3-STATE Outputs
April 1988
Revised September 2000
74F350
4-Bit Shifter with 3-STATE Outputs
General Description
The 74F350 is a specialized multiplexer that accepts a 4-bit
word and shifts it 0, 1, 2 or 3 places, as determined by two
Select (S
0
, S
1
) inputs. For expansion to longer words, three
linking inputs are provided for lower-order bits; thus two
packages can shift an 8-bit word, four packages a 16-bit
word, etc. Shifting by more than three places is accom-
plished by paralleling the 3-STATE outputs of different
packages and using the Output Enable (OE) inputs as a
third Select level. With appropriate interconnections, the
74F350 can perform zero-backfill, sign-extend or end-
around (barrel) shift functions.
Features
s
Linking inputs for word expansion
s
3-STATE outputs for extending shift range
Ordering Code:
Order Number
74F350SC
74F350SJ
74F350PC
Package Number
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Truth Table
Inputs
OE
H
L
L
L
L
S
1
X
L
L
H
H
S
0
X
L
H
L
H
O
0
Z
I
0
I
−1
I
−2
I
−3
Outputs
O
1
Z
I
1
I
0
I
−1
I
−2
O
2
Z
I
2
I
1
I
0
I
−1
O
3
Z
I
3
I
2
I
1
I
0
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
© 2000 Fairchild Semiconductor Corporation
DS009518
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74F350
Unit Loading/Fan Out
Pin Names
S
0
, S
1
I
−3
–I
3
OE
O
0
–O
3
Description
Select Inputs
Data Inputs
Output Enable Input (Active LOW)
3-STATE Outputs
U.L.
HIGH/LOW
1.0/2.0
1.0/2.0
1.0/2.0
150/40 (33.3)
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
1.2 mA
20
µ
A/
−
1.2 mA
20
µ
A/
−
1.2 mA
−
3 mA/24 mA (20 mA)
Functional Description
The 74F350 is operationally equivalent to a 4-input multi-
plexer with the inputs connected so that the select code
causes successive one-bit shifts of the data word. This
internal connection makes it possible to perform shifts of 0,
1, 2 or 3 places on words of any length.
A 4-bit data word is introduced at the I
n
inputs and is
shifted according to the code applied to the select inputs
S
0
, S
1
. Outputs O
0
–O
3
are 3-STATE, controlled by an
active LOW output enable (OE). When OE is LOW, data
outputs will follow selected data inputs; when HIGH, the
data outputs will be forced to the high impedance state.
This feature allows shifters to be cascaded on the same
output lines or to a common bus. The shift function can be
logical, with zeros pulled in at either or both ends of the
shifting field; arithmetic, where the sign bit is repeated dur-
ing a shift down; or end around, where the data word forms
a continuous loop.
Logic Equations
O
0
=
S
0
S
1
I
0
+
S
0
S
1
I
−1
+
S
0
S
1
I
−2
+
S
0
S
1
I
−3
O
1
=
S
0
S
1
I
1
+
S
0
S
1
I
0
+
S
0
S
1
I
−1
+
S
0
S
1
I
−2
O
2
=
S
0
S
1
I
2
+
S
0
S
1
I
1
+
S
0
S
1
I
0
+
S
0
S
1
I
−1
O
3
=
S
0
S
1
I
3
+
S
0
S
1
I
2
+
S
0
S
1
I
1
+
S
0
S
1
I
0
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74F350
Applications
16-Bit Shift-Up 0 to 3 Places, Zero Backfill
Function Table
S
1
L
L
H
H
S
0
L
H
L
H
No Shift
Shift 1 Place
Shift 2 Places
Shift 3 Places
Shift Function
8-Bit End Around Shift 0 to 7 Places
Function Table
S
2
L
L
L
L
H
H
H
H
S
1
L
L
H
H
L
L
H
H
S
0
L
H
L
H
L
H
L
H
Shift Function
No Shift
Shift End Around 1
Shift End Around 2
Shift End Around 3
Shift End Around 4
Shift End Around 5
Shift End Around 6
Shift End Around 7
3
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74F350
13-Bit Twos Complement Scaler
Function Table
S
1
L
L
H
H
L
÷
8
H
÷
4
L
÷
2
H No Change
S
0
Scale
1
1
/
8
/
4
½
1
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4
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