74ACTQ74 Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
May 2007
74ACTQ74
Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
Features
■
I
CC
reduced by 50%
■
Guaranteed simultaneous switching noise level and
■
■
■
■
tm
General Description
The 74ACTQ74 is a dual D-type flip-flop with Asynchro-
nous Clear and Set inputs and complementary (Q, Q)
outputs. Information at the input is transferred to the
outputs on the positive edge of the clock pulse. Clock
triggering occurs at a voltage level of the clock pulse and
is not directly related to the transition time of the positive-
going pulse. After the Clock Pulse input threshold volt-
age has been passed, the Data input is locked out and
information present will not be transferred to the outputs
until the next rising edge of the Clock Pulse input.
The ACTQ74 utilizes Fairchild Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series™ features
GTO™ output control and undershoot corrector in addi-
tion to a split ground bus for superior performance.
Asynchronous Inputs:
■
LOW input to S
D
(Set) sets Q to HIGH level
■
LOW input to C
D
(Clear) sets Q to LOW level
■
Clear and Set are independent of clock
■
Simultaneous LOW on C
D
and S
D
makes both Q and
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
4kV minimum ESD immunity
TTL-compatible inputs
Q HIGH
Ordering Information
Order
Number
74ACTQ74SC
74ACTQ74SJ
Package
Number
M14A
M14D
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Descriptions
Pin Names
D
1
, D
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
1
, Q
2
, Q
2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACT™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
©1993 Fairchild Semiconductor Corporation
74ACTQ74 Rev. 1.4
www.fairchildsemi.com
74ACTQ74 Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
Logic Symbols
Truth Table
(Each Half)
Inputs
S
D
L
H
L
H
H
H
IEEE/IEC
Outputs
D
X
X
X
H
L
L
X
C
D
H
L
L
H
H
H
CP
X
X
X
Q
H
L
H
H
L
Q
0
Q
L
H
H
L
H
Q
0
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Q
0
(Q
0
)
=
Previous Q(Q) before LOW-to-HIGH Transition
of Clock
Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1993 Fairchild Semiconductor Corporation
74ACTQ74 Rev. 1.4
www.fairchildsemi.com
2
74ACTQ74 Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5V
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±50mA
±50mA
–65°C to +150°C
±300mA
140°C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
DC Latch-Up Source or Sink Current
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
V
O
T
A
∆
V /
∆
t
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Minimum Input Edge Rate:
Parameter
Rating
4.5V to 5.5V
0V to V
CC
0V to V
CC
–40°C to +85°C
125mV/ns
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1993 Fairchild Semiconductor Corporation
74ACTQ74 Rev. 1.4
www.fairchildsemi.com
3
74ACTQ74 Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
DC Electrical Characteristics
T
A
=
+25°C T
A
=
–40°C to +85°C
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
Conditions
V
OUT
=
0.1V
or V
CC
– 0.1V
V
OUT
=
0.1V
or V
CC
– 0.1V
I
OUT
=
–50 µA
V
IN
=
V
IL
or V
IH
:
I
OH
= –24mA
I
OH
= –24mA
(1)
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
Typ.
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
±5.0
1.5
75
–75
2.0
20.0
Units
V
V
V
3.86
4.86
0.001
0.001
0.1
0.1
0.36
0.36
±0.1
±0.5
0.6
V
OL
Maximum LOW Level
Output Voltage
I
OUT
=
50µA
V
IN
=
V
IL
or V
IH
:
I
OL
= 24mA
I
OL
= 24mA
(1)
V
4.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
1.1
–0.6
1.9
1.2
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current
(1)
Maximum Quiescent
Supply Current
V
I
=
V
CC
, GND
V
I
=
V
IL
, V
IH
;
V
O
=
V
CC
, GND
V
I
=
V
CC
– 2.1V
V
OLD
=
1.65V Max.
V
OHD
=
3.85V Min.
V
IN
=
V
CC
or GND
µA
µA
mA
mA
mA
µA
V
V
V
V
Quiet Output Maximum Figures 1 & 2
(3)
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
Figures 1 & 2
(3)
(4)
1.5
–1.2
2.2
0.8
(4)
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
4. Max number of data inputs (n) switching. (n – 1) inputs switching 0V to 3V. Input-under-test switching:
3V to threshold (V
ILD
), 0V to threshold (V
IHD
), f
=
1MHz.
©1993 Fairchild Semiconductor Corporation
74ACTQ74 Rev. 1.4
www.fairchildsemi.com
4
74ACTQ74 Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop
AC Electrical Characteristics
T
A
=
+25°C,
C
L
=
50pF
Symbol
f
MAX
t
PLH
, t
PHL
t
PLH
, t
PHL
T
A
=
–40°C to +85°C,
C
L
=
50pF
Min.
125
3.0
3.0
Parameter
Maximum Clock Frequency
Propagation Delay,
C
Dn
or S
Dn
to Q
n
or Q
n
Propagation Delay,
CP
n
to Q
n
or Q
n
V
CC
(V)
(5)
5.0
5.0
5.0
5.0
Min.
145
3.0
3.0
Typ.
200
7.0
6.5
0.5
Max.
8.5
8.0
1.0
Max.
9.0
8.6
1.0
Units
MHz
ns
ns
ns
t
OSLH
, t
OSHL
Output to Output Skew
(6)
Notes:
5. Voltage range 5.0 is 5.0V ± 0.5V.
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate
outputs of the same device. The specification applies to any outputs switching in the same direction, either
HIGH-to-LOW (t
OSHL
) or LOW
-
to-HIGH (t
OSLH
). Parameter guaranteed by design.
AC Operating Requirements
T
A
=
+25°C,
C
L
=
50pF
Symbol
t
S
t
H
t
W
t
REC
T
A
=
–40°C to +85°C,
C
L
=
50pF
Guaranteed Minimum
Units
ns
ns
ns
ns
3.0
1.5
4.0
1.5
Parameter
Setup Time, HIGH or LOW,
D
n
to CP
n
Hold Time, HIGH or LOW,
D
n
to CP
n
CP
n
or C
Dn
or S
Dn
,
Pulse Width
Recovery Time,
C
Dn
or S
Dn
to CP
V
CC
(V)
(7)
5.0
5.0
5.0
5.0
Typ.
1.0
–0.5
3.0
–2.5
3.0
1.5
4.0
1.5
Note:
7. Voltage range 5.0 is 5.0V ± 0.5V.
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Conditions
V
CC
=
OPEN
V
CC
=
5.0V
Typ.
4.5
60.0
Units
pF
pF
©1993 Fairchild Semiconductor Corporation
74ACTQ74 Rev. 1.4
www.fairchildsemi.com
5
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